#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf))
#define SMI_PORT0_15_POLLING_SEL 0xca08
#define SMI_ACCESS_PHY_CTRL_0 0xcb70
-#define SMI_ACCESS_PHY_CTRL_1 0xcb74
+#define RTL9300_SMI_ACCESS_PHY_CTRL_1 0xcb74
#define PHY_CTRL_REG_ADDR GENMASK(24, 20)
#define PHY_CTRL_PARK_PAGE GENMASK(19, 15)
#define PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
struct otto_emdio_cmd_regs {
+ u32 c22_data;
u32 c45_data;
};
static int otto_emdio_wait_ready(struct otto_emdio_priv *priv)
{
struct regmap *regmap = priv->regmap;
- u32 val;
+ u32 cmd_reg, val;
lockdep_assert_held(&priv->lock);
+ cmd_reg = priv->info->cmd_regs.c22_data; /* shared command/C22 register */
- return regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
- val, !(val & PHY_CTRL_CMD), 10, 1000);
+ return regmap_read_poll_timeout(regmap, cmd_reg, val, !(val & PHY_CTRL_CMD), 10, 1000);
}
static int otto_emdio_9300_read_c22(struct mii_bus *bus, int phy_id, int regnum)
struct otto_emdio_chan *chan = bus->priv;
struct otto_emdio_priv *priv;
struct regmap *regmap;
+ u32 cmd_reg, val;
int port;
- u32 val;
int err;
priv = chan->priv;
regmap = priv->regmap;
+ cmd_reg = priv->info->cmd_regs.c22_data; /* shared command/C22 register */
port = otto_emdio_phy_to_port(bus, phy_id);
if (port < 0)
FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)) |
PHY_CTRL_READ | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
- err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
+ err = regmap_write(regmap, cmd_reg, val);
if (err)
goto out_err;
struct otto_emdio_chan *chan = bus->priv;
struct otto_emdio_priv *priv;
struct regmap *regmap;
+ u32 cmd_reg, val;
int port;
- u32 val;
int err;
priv = chan->priv;
regmap = priv->regmap;
+ cmd_reg = priv->info->cmd_regs.c22_data; /* shared command/C22 register */
port = otto_emdio_phy_to_port(bus, phy_id);
if (port < 0)
FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)) |
PHY_CTRL_WRITE | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
- err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
+ err = regmap_write(regmap, cmd_reg, val);
if (err)
goto out_err;
- err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
- val, !(val & PHY_CTRL_CMD), 10, 100);
+ err = regmap_read_poll_timeout(regmap, cmd_reg, val, !(val & PHY_CTRL_CMD), 10, 100);
if (err)
goto out_err;
struct otto_emdio_chan *chan = bus->priv;
struct otto_emdio_priv *priv;
struct regmap *regmap;
+ u32 cmd_reg, val;
int port;
- u32 val;
int err;
priv = chan->priv;
regmap = priv->regmap;
+ cmd_reg = priv->info->cmd_regs.c22_data; /* shared command/C22 register */
port = otto_emdio_phy_to_port(bus, phy_id);
if (port < 0)
if (err)
goto out_err;
- err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
- PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD);
+ err = regmap_write(regmap, cmd_reg, PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD);
if (err)
goto out_err;
struct otto_emdio_chan *chan = bus->priv;
struct otto_emdio_priv *priv;
struct regmap *regmap;
+ u32 cmd_reg, val;
int port;
- u32 val;
int err;
priv = chan->priv;
regmap = priv->regmap;
+ cmd_reg = priv->info->cmd_regs.c22_data; /* shared command/C22 register */
port = otto_emdio_phy_to_port(bus, phy_id);
if (port < 0)
if (err)
goto out_err;
- err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
- PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD);
+ err = regmap_write(regmap, cmd_reg, PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD);
if (err)
goto out_err;
- err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
- val, !(val & PHY_CTRL_CMD), 10, 100);
+ err = regmap_read_poll_timeout(regmap, cmd_reg, val, !(val & PHY_CTRL_CMD), 10, 100);
if (err)
goto out_err;
static const struct otto_emdio_info otto_emdio_9300_info = {
.cmd_regs = {
+ .c22_data = RTL9300_SMI_ACCESS_PHY_CTRL_1,
.c45_data = RTL9300_SMI_ACCESS_PHY_CTRL_3,
},
.num_buses = RTL9300_NUM_BUSES,