]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card
authorSarthak Garg <quic_sartgarg@quicinc.com>
Mon, 8 Sep 2025 10:41:19 +0000 (16:11 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 13 Nov 2025 20:36:50 +0000 (15:36 -0500)
[ Upstream commit 08b68ca543ee9d5a8d2dc406165e4887dd8f170b ]

For Qualcomm SoCs which needs level shifter for SD card, extra delay is
seen on receiver data path.

To compensate this delay enable tuning for SDR50 mode for targets which
has level shifter. SDHCI_SDR50_NEEDS_TUNING caps will be set for targets
with level shifter on Qualcomm SOC's.

Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/mmc/host/sdhci-msm.c

index 9d8e20dc8ca11a523daf1ec1b8b7cb1935f06327..e7df864bdcaf6b00a65ecc454eb1f3f9d64c2f20 100644 (file)
@@ -81,6 +81,7 @@
 #define CORE_IO_PAD_PWR_SWITCH_EN      BIT(15)
 #define CORE_IO_PAD_PWR_SWITCH BIT(16)
 #define CORE_HC_SELECT_IN_EN   BIT(18)
+#define CORE_HC_SELECT_IN_SDR50        (4 << 19)
 #define CORE_HC_SELECT_IN_HS400        (6 << 19)
 #define CORE_HC_SELECT_IN_MASK (7 << 19)
 
@@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
 {
        struct mmc_ios *ios = &host->mmc->ios;
 
+       if (ios->timing == MMC_TIMING_UHS_SDR50 &&
+           host->flags & SDHCI_SDR50_NEEDS_TUNING)
+               return true;
+
        /*
         * Tuning is required for SDR104, HS200 and HS400 cards and
         * if clock frequency is greater than 100MHz in these modes.
@@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
        struct mmc_ios ios = host->mmc->ios;
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
        struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+       const struct sdhci_msm_offset *msm_offset = msm_host->offset;
+       u32 config;
 
        if (!sdhci_msm_is_tuning_needed(host)) {
                msm_host->use_cdr = false;
@@ -1217,6 +1224,14 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
         */
        msm_host->tuning_done = 0;
 
+       if (ios.timing == MMC_TIMING_UHS_SDR50 &&
+           host->flags & SDHCI_SDR50_NEEDS_TUNING) {
+               config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
+               config &= ~CORE_HC_SELECT_IN_MASK;
+               config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50;
+               writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
+       }
+
        /*
         * For HS400 tuning in HS200 timing requires:
         * - select MCLK/2 in VENDOR_SPEC