drm/i915/psr: Compute PSR entry_setup_frames into intel_crtc_state

PSR entry_setup_frames is currently computed directly into struct
intel_dp:intel_psr:entry_setup_frames. This causes a problem if mode change
gets rejected after PSR compute config: Psr_entry_setup_frames computed for
this rejected state is in intel_dp:intel_psr:entry_setup_frame. Fix this by
computing it into intel_crtc_state and copy the value into
intel_dp:intel_psr:entry_setup_frames on PSR enable.

Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier")
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: <stable@vger.kernel.org> # v6.8+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312083710.1593781-3-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e189f8c39ccb440f99cd642de177b18f3b605753..d3a9ace4c9d13b9699cbf4d27576e4d8eccb3674 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1188,6 +1188,7 @@ struct intel_crtc_state {
        u32 dc3co_exitline;
        u16 su_y_granularity;
        u8 active_non_psr_pipes;
+       u8 entry_setup_frames;
        const char *no_psr_reason;
 
        /*

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7e0e4c3bf985e164c55fb1e1da83bf2446b25a96..c13116e6f17f270fcc5a88eb442bdcd8d3ce2653 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1716,7 +1716,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
        entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
 
        if (entry_setup_frames >= 0) {
-               intel_dp->psr.entry_setup_frames = entry_setup_frames;
+               crtc_state->entry_setup_frames = entry_setup_frames;
        } else {
                crtc_state->no_psr_reason = "PSR setup timing not met";
                drm_dbg_kms(display->drm,
@@ -1814,7 +1814,7 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
 {
        struct intel_display *display = to_intel_display(intel_dp);
 
-       return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&
+       return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
                !crtc_state->has_sel_update);
 }
 
@@ -2190,6 +2190,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
        intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
        intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;
        intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;
+       intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
 
        if (!psr_interrupt_error_check(intel_dp))
                return;