pinctrl: samsung: Add Exynos9610 pinctrl configuration

Add pinctrl configuration for Exynos9610. The bank types used are the
same as on Exynos850 and gs101, so we can reuse the macros.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
Link: https://patch.msgid.link/20260102-exynos9610-pinctrl-v3-3-3f21f2cfb651@chimac.ro
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 627dca504d7a924f273abd3796e87c816d9be535..fe9f92cb037ead2c9a48279a3ea45beb46a229a3 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -1770,6 +1770,123 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = {
        .num_ctrl       = ARRAY_SIZE(exynos8895_pin_ctrl),
 };
 
+/* pin banks of exynos9610 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks0[] __initconst = {
+       EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"),
+       GS101_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00, 0x00),
+       GS101_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04, 0x08),
+       GS101_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08, 0x0c),
+       EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"),
+};
+
+/* pin banks of exynos9610 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks1[] __initconst = {
+       EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60),
+       EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64),
+};
+
+/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks2[] __initconst = {
+       GS101_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00, 0x00),
+       GS101_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04, 0x08),
+       GS101_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08, 0x0c),
+};
+
+/* pin banks of exynos9610 pin-controller 3 (FSYS) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks3[] __initconst = {
+       GS101_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00, 0x00),
+       GS101_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04, 0x04),
+       GS101_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08, 0x0c),
+};
+
+/* pin banks of exynos9610 pin-controller 4 (TOP) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks4[] __initconst = {
+       GS101_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00, 0x00),
+       GS101_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04, 0x08),
+       GS101_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08, 0x10),
+       GS101_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C, 0x18),
+       GS101_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10, 0x20),
+       GS101_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14, 0x28),
+       GS101_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18, 0x30),
+       GS101_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C, 0x38),
+       GS101_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20, 0x40),
+       GS101_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24, 0x48),
+       GS101_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28, 0x50),
+};
+
+/* pin banks of exynos9610 pin-controller 5 (SHUB) */
+static const struct samsung_pin_bank_data exynos9610_pin_banks5[] __initconst = {
+       EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00),
+       EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04),
+};
+
+static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst = {
+       {
+               /* pin-controller instance 0 ALIVE data */
+               .pin_banks      = exynos9610_pin_banks0,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks0),
+               .eint_wkup_init = exynos_eint_wkup_init,
+               .suspend        = exynos_pinctrl_suspend,
+               .resume         = exynos_pinctrl_resume,
+       }, {
+               /* pin-controller instance 1 CMGP data */
+               .pin_banks      = exynos9610_pin_banks1,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks1),
+               .eint_wkup_init = exynos_eint_wkup_init,
+               .suspend        = exynos_pinctrl_suspend,
+               .resume         = exynos_pinctrl_resume,
+       }, {
+               /* pin-controller instance 2 DISPAUD data */
+               .pin_banks      = exynos9610_pin_banks2,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks2),
+       }, {
+               /* pin-controller instance 3 FSYS data */
+               .pin_banks      = exynos9610_pin_banks3,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks3),
+               .suspend        = exynos_pinctrl_suspend,
+               .resume         = exynos_pinctrl_resume,
+       }, {
+               /* pin-controller instance 4 TOP data */
+               .pin_banks      = exynos9610_pin_banks4,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks4),
+               .suspend        = exynos_pinctrl_suspend,
+               .resume         = exynos_pinctrl_resume,
+       }, {
+               /* pin-controller instance 5 SHUB data */
+               .pin_banks      = exynos9610_pin_banks5,
+               .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks5),
+       },
+};
+
+const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = {
+       .ctrl           = exynos9610_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos9610_pin_ctrl),
+};
+
 /*
  * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
  * gpio/pin-mux/pinconfig controllers.

diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e374effba25a76cdd69fb5da8d80dd8cf660298a..5ac6f6b02327276f3224706df0d9658b97a6f87f 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1504,6 +1504,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
                .data = &exynos8890_of_data },
        { .compatible = "samsung,exynos8895-pinctrl",
                .data = &exynos8895_of_data },
+       { .compatible = "samsung,exynos9610-pinctrl",
+               .data = &exynos9610_of_data },
        { .compatible = "samsung,exynos9810-pinctrl",
                .data = &exynos9810_of_data },
        { .compatible = "samsung,exynos990-pinctrl",

diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 0f7b2ea981586800ecf7f40b81c51b339ffb538f..937600430a6ef9154d9685d1c26803d596b0cfba 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -398,6 +398,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;