arm64: dts: socfpga: agilex5: Add dma-coherent property

Add the `dma-coherent` property to these device nodes to inform the
kernel and DMA subsystem that the devices support hardware-managed
cache coherence.

Changes:
 - Add `dma-coherent` to `cdns,hp-nfc`
 - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances
   (dmac0, dmac1)

This aligns the Agilex5 device tree with the coherent DMA-capable
devices accordingly.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a5c2025a616e896e25335b8403143f4edcac7d02..89a2ff59554b22c578da7558ad48ff8ded4824bb 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -312,6 +312,7 @@
                        clock-names = "nf_clk";
                        cdns,board-delay-ps = <4830>;
                        iommus = <&smmu 4>;
+                       dma-coherent;
                        status = "disabled";
                };
 
@@ -339,6 +340,7 @@
                        snps,priority = <0 1 2 3>;
                        snps,axi-max-burst-len = <8>;
                        iommus = <&smmu 8>;
+                       dma-coherent;
                };
 
                dmac1: dma-controller@10dc0000 {
@@ -357,6 +359,7 @@
                        snps,priority = <0 1 2 3>;
                        snps,axi-max-burst-len = <8>;
                        iommus = <&smmu 9>;
+                       dma-coherent;
                };
 
                rst: rstmgr@10d11000 {