RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2...

Add asm dump check test for vec_duplicate + vxor.vv combine to vxor.vx,
with the GR2VR cost is 0, 2 and 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vxor.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for vxor run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index b15cb4cb8e6f6ae3c49841d7990fdcaf5b15a8d3..b9be0f674aec4325c7b9e8cebd88cc16499e5881 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index df3d3a33a34221a004d7e17b2b6aba624a93a31d..2a84980cb503b040f2e1d78723e20f8390048c08 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index ed17b83157769a46d1e01345554f5319e55ce79e..9c7ea5fa41322cc1d05a2ecfd2e1fa6d6f79855c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index aa11dafc677fec6d23db18f07a223dadb8dab942..fc23f1c49f962f64605a04081c570e8f23acf76a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 15db5887a035360d6fae181ef4cfd0cd896c1c78..7e107d30191d0219c48b08fe6ca8cd413eee52ba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index f15592c40eb2e7df4f1ed3139fbe7a07d71cec5a..f8ffab78067a26d8c4797f9c9570624afebd8164 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 80e32afe8435749a89f18e92bd8cdcf173d91019..31d294567e8314171fa83fb9dbff0c15bca19ba2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 9b19276f2e6b89d747200c850536c84c893b42d3..59e033401b21cf484482a74156497c140929ff95 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 596488c877030d5e63b6955bb687fae32caac1bc..de250864e2d207bb0d61ba0094c751219fca4524 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 8b4b7ebd2897df831f5bb4d9b69842dade389ef7..5cac7c685f6651170db3cb1de4380563f7bfb5b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 544c9074a15c3076685f8bdf78b4ef298e208cef..4b2885a0da914ba391e59f94ec872991bbba2310 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index af53f2b9ca43b47c1d08957d0bdf5237abf2bb80..e14683198e549b81cc3cc971ca28b4d4873e4190 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a8ff915d7073a07736e6ce6698785953b55e0404..9612e3f66cc4456f846481958d75a1056a7c89f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index d587a88463e10838da3fa465845d1c6cca4469e2..964180243b47261b8255486ab90adf402d7f229f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index ff205d53a55fe2b809a48520814279494f1e09cb..0d173e0dbbb904822bf8a6ba2260ce82d2abce61 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index e8e2c7fb6e70453487792fb10b13676012964918..931295ec0fb3bd4420dfb69626c4ca4292d75bba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index bd38b86bc552ad5a1624b68c56c2a6ee7d852ed4..d9e6e7b03891e6cf715d6ab05247d8d128808a36 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e0bdd2259fac024faf6c2e226db55ae5c56ec1e4..13d219ec73ad361b4f56495158d914167a321184 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index aab3b4afc7ff10ebcb943780a830d7eb49b7bbb6..037a713a60dd59457f2875a15314a27a6ba1f640 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 825988b04ccea321c6789bd89a591f864211adbe..c97fff4b09f5ea08e23b1f6ab05c0455283d03ca 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a750510c1cee969495f5cd4abde944e3a349b252..24b4aa7efba19ddb50a103d89ef8d7d1f57cc82f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 2d279cfa478fcef00625c2b3c261c476d08c63d0..0c1552a2054139c82011ec96520bef410e6f3e79 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 5a90883c1df4922b4fbde7d413e4764e1a5d6a0b..8364f19b1787ab92bfbdec747d1a3b2d54f790a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 69af97a3a994c292764317f22b6b1a1312c284e0..8a3111157ffe08b17c864761aee6c4dc1fa2b38f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index cd3cede15c82fe8694d7a92cad58ee6b9747ab27..60f47f864bcd81f2a6f5aec8841cd294e39ce9e2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1966,4 +1966,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xfe, 0xfe, 0xfe, 0xfe,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+      0x70, 0x70, 0x70, 0x70,
+       0xf,  0xf,  0xf,  0xf,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+       0xf,  0xf,  0xf,  0xf,
+      0xef, 0xef, 0xef, 0xef,
+      0x70, 0x70, 0x70, 0x70,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0x0fff, 0x0fff, 0x0fff, 0x0fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+         0xf,    0xf,    0xf,    0xf,
+      0xffef, 0xffef, 0xffef, 0xffef,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+       0xfffffff,  0xfffffff,  0xfffffff,  0xfffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+             0xf,        0xf,        0xf,        0xf,
+      0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+       0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xfe, 0xfe, 0xfe, 0xfe,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+      0x70, 0x70, 0x70, 0x70,
+       0xf,  0xf,  0xf,  0xf,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+       0xf,  0xf,  0xf,  0xf,
+      0xef, 0xef, 0xef, 0xef,
+      0x70, 0x70, 0x70, 0x70,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0x0fff, 0x0fff, 0x0fff, 0x0fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+         0xf,    0xf,    0xf,    0xf,
+      0xffef, 0xffef, 0xffef, 0xffef,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+       0xfffffff,  0xfffffff,  0xfffffff,  0xfffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+             0xf,        0xf,        0xf,        0xf,
+      0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+       0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
new file mode 100644 (file)
index 0000000..8441720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
new file mode 100644 (file)
index 0000000..cdb773f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
new file mode 100644 (file)
index 0000000..8618b9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
new file mode 100644 (file)
index 0000000..13724ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
new file mode 100644 (file)
index 0000000..e6030f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
new file mode 100644 (file)
index 0000000..cdb773f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
new file mode 100644 (file)
index 0000000..44f0fff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
new file mode 100644 (file)
index 0000000..2e983e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"