arm64: dts: imx93-11x11-frdm: Add MQS audio support

Enable Medium Quality Sound (MQS) output on the i.MX93 FRDM 11x11 board
by adding sound card description and enabling sai1 and mqs1 dts nodes,
together with necessary clocks and pinmux.

This supports audio playback via SAI1 DAI which is connected to the MQS1
block.

Co-developed-by: Tom Zheng <haidong.zheng@nxp.com>
Signed-off-by: Tom Zheng <haidong.zheng@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Tested-by: Francesco Valla <francesco@valla.it>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
index 066c5139842bd277c6564a7e3df267149c692721..5bb6ae0d154a655283295b6902fc29bf6f744d5c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
@@ -81,6 +81,13 @@
                        no-map;
                };
        };
+
+       sound-mqs {
+               compatible = "fsl,imx-audio-mqs";
+               model = "mqs-audio";
+               audio-cpu = <&sai1>;
+               audio-codec = <&mqs1>;
+       };
 };
 
 &adc1 {
@@ -315,6 +322,27 @@
        status = "okay";
 };
 
+&mqs1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_mqs1>;
+       clocks = <&clk IMX93_CLK_MQS1_GATE>;
+       clock-names = "mclk";
+       status = "okay";
+};
+
+&sai1 {
+       #sound-dai-cells = <0>;
+       clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+                <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+                <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
+       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
+       assigned-clocks = <&clk IMX93_CLK_SAI1>;
+       assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+       assigned-clock-rates = <24576000>;
+       fsl,sai-mclk-direction-output;
+       status = "okay";
+};
+
 &usbotg1 {
        adp-disable;
        disable-over-current;
@@ -479,6 +507,13 @@
                >;
        };
 
+       pinctrl_mqs1: mqs1grp {
+               fsl,pins = <
+                       MX93_PAD_PDM_CLK__MQS1_LEFT             0x31e
+                       MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT    0x31e
+               >;
+       };
+
        pinctrl_pcal6524: pcal6524grp {
                fsl,pins = <
                        MX93_PAD_CCM_CLKO2__GPIO3_IO27                  0x31e