else
buf_size = priv->dma_conf.dma_buf_sz;
- stmmac_set_dma_bfsize(priv, priv->ioaddr, buf_size, rx_q->queue_index);
+ stmmac_set_dma_bfsize(priv, priv->ioaddr, buf_size, chan);
}
/**
NULL));
netdev_info(priv->dev,
"Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
- rx_q->queue_index);
+ queue);
xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
} else {
WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
rx_q->page_pool));
netdev_info(priv->dev,
"Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
- rx_q->queue_index);
+ queue);
}
if (rx_q->xsk_pool) {
else
napi_id = ch->rx_napi.napi_id;
- ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
- rx_q->queue_index,
- napi_id);
+ ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, queue, napi_id);
if (ret) {
netdev_err(priv->dev, "Failed to register xdp rxq info\n");
return -EINVAL;
if (!tx_coal_timer)
return;
- ch = &priv->channel[tx_q->queue_index];
+ ch = &priv->channel[queue];
napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
/* Arm timer only if napi is not already scheduled.
stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue);
stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
- rx_q->dma_rx_phy, rx_q->queue_index);
+ rx_q->dma_rx_phy, queue);
- stmmac_set_queue_rx_tail_ptr(priv, rx_q, rx_q->queue_index,
- rx_q->buf_alloc_num);
+ stmmac_set_queue_rx_tail_ptr(priv, rx_q, queue, rx_q->buf_alloc_num);
- stmmac_set_queue_rx_buf_size(priv, rx_q, rx_q->queue_index);
+ stmmac_set_queue_rx_buf_size(priv, rx_q, queue);
stmmac_start_rx_dma(priv, queue);
stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue);
stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
- tx_q->dma_tx_phy, tx_q->queue_index);
+ tx_q->dma_tx_phy, queue);
if (tx_q->tbs & STMMAC_TBS_AVAIL)
- stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
+ stmmac_enable_tbs(priv, priv->ioaddr, 1, queue);
- stmmac_set_queue_tx_tail_ptr(priv, tx_q, tx_q->queue_index, 0);
+ stmmac_set_queue_tx_tail_ptr(priv, tx_q, queue, 0);
stmmac_start_tx_dma(priv, queue);