]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
KVM: x86: Move open-coded CPUID leaf 0x80000021 EAX bit propagation code
authorKim Phillips <kim.phillips@amd.com>
Fri, 12 Sep 2025 22:29:13 +0000 (18:29 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 19 Sep 2025 14:29:56 +0000 (16:29 +0200)
Commit c35ac8c4bf600ee23bacb20f863aa7830efb23fb upstream

Move code from __do_cpuid_func() to kvm_set_cpu_caps() in preparation for adding
the features in their native leaf.

Also drop the bit description comments as it will be more self-describing once
the individual features are added.

Whilst there, switch to using the more efficient cpu_feature_enabled() instead
of static_cpu_has().

Note, LFENCE_RDTSC and "NULL selector clears base" are currently synthetic,
Linux-defined feature flags as Linux tracking of the features predates AMD's
definition.  Keep the manual propagation of the flags from their synthetic
counterparts until the kernel fully converts to AMD's definition, otherwise KVM
would stop synthesizing the flags as intended.

Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20230124163319.2277355-3-kim.phillips@amd.com
Move setting of VERW_CLEAR bit to the new
kvm_cpu_cap_mask(CPUID_8000_0021_EAX, ...) site.

Cc: <stable@vger.kernel.org> # 6.1.y
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/kvm/cpuid.c

index 1bb5e8f6c63e4750ec87098292503738ca832be6..4f60341b1e94b342d677e898a9ad4ea166937ed6 100644 (file)
@@ -749,6 +749,18 @@ void kvm_set_cpu_caps(void)
                0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
                F(SME_COHERENT));
 
+       kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
+               BIT(0) /* NO_NESTED_DATA_BP */ |
+               BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
+               BIT(5) /* The memory form of VERW mitigates TSA */ |
+               BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
+       );
+       if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
+               kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */;
+       if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
+               kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
+       kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
+
        kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
                F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
                F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
@@ -758,8 +770,6 @@ void kvm_set_cpu_caps(void)
        if (cpu_feature_enabled(X86_FEATURE_SRSO_NO))
                kvm_cpu_cap_set(X86_FEATURE_SRSO_NO);
 
-       kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(VERW_CLEAR));
-
        kvm_cpu_cap_init_kvm_defined(CPUID_8000_0021_ECX,
                F(TSA_SQ_NO) | F(TSA_L1_NO)
        );
@@ -1249,23 +1259,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
                entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
                break;
        case 0x80000021:
-               entry->ebx = entry->edx = 0;
-               /*
-                * Pass down these bits:
-                *    EAX      0      NNDBP, Processor ignores nested data breakpoints
-                *    EAX      2      LAS, LFENCE always serializing
-                *    EAX      6      NSCB, Null selector clear base
-                *
-                * Other defined bits are for MSRs that KVM does not expose:
-                *   EAX      3      SPCL, SMM page configuration lock
-                *   EAX      13     PCMSR, Prefetch control MSR
-                */
-               entry->eax &= BIT(0) | BIT(2) | BIT(6);
-               if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-                       entry->eax |= BIT(2);
-               if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
-                       entry->eax |= BIT(6);
-               cpuid_entry_override(entry, CPUID_8000_0021_ECX);
+               entry->ebx = entry->ecx = entry->edx = 0;
+               cpuid_entry_override(entry, CPUID_8000_0021_EAX);
                break;
        /*Add support for Centaur's CPUID instruction*/
        case 0xC0000000: