RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1...

Add asm dump check test for vec_duplicate + vrem.vv combine to vrem.vx,
with the GR2VR cost is 0, 1 and 2.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
	for vrem.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
index 1e409dea08b79d86e16f0b4c868dc1b68f39fce4..b35e4b712f0815df300b16e40b44487f011b4b4f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
index 2f242c73717e57a8f9d65897cf417c05932b662d..fb01a6ab92d9a7bac71fe62e79617e5b76b7deb6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
index f027bd8129e498559043de18fc7da21886bfb9ed..d9341d6b4d24fdc18ab4299d1171a610b48c2b8d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
index c4f55b0228eb3ab3275783cac938c26115532f96..02fdecea8e5572574d2ecf057fa5d8dfcee3bad7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index d6b05bc875c058f7551529d55b1ead02283e6813..a9ea0820b9475bf210aeab340bb5e8f2ee664b42 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
index e1c043fbb45866f8580362eae210025b4696f515..aaf37c5ea0e62ff494685d838cf5c84555c0fc89 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
index 1beb9146d049f220fce39a034121197a59e94683..4f80dab98e078034be0891f06da6065894bcb98d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 0291517d727e1425cc949e4337dc1378bf3b8725..85ef4f1fd632bb37a771e3d6ab1c16e78c300903 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index c22c82dce1b4a8cbec7d91844c0a7dc358af84ec..3ac50413d2daa4ffbb36bc154948ae77629dce30 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index dc3560070afd7c313ef43b192bbd83ea23b7d7de..32ce58aa486715975a366bd7f27c3edb47ebd21f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index cee1e3a819bfc509d8cbb23fefe21267df5ba245..722282a5b63a07bb9f7a73c7242a737d03e9598e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 74fd2fb9a5792cea3b76539084a38d636744c4c2..27dffc7b3d095395bdae24965ba78ac811cab33c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
 /* { dg-final { scan-assembler {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler {vdiv.vx} } } */
+/* { dg-final { scan-assembler {vrem.vx} } } */