i386: Fix vec_set<mode> expanders [PR101424]

AVX does not support 32-byte integer compares, required by
ix86_expand_vector_set_var.  The following patch fixes vec_set<mode>
expanders by introducing new vec_setm_avx2_operand predicate for AVX
vector modes.

gcc/

2021-07-12  Uroš Bizjak  <ubizjak@gmail.com>

	PR target/101424
	* config/i386/predicates.md (vec_setm_sse41_operand):
	Rename from vec_setm_operand.
	(vec_setm_avx2_operand): New predicate.
	* config/i386/sse.md (vec_set<V_128:mode>): Use V_128 mode iterator.
	Use vec_setm_sse41_operand as operand 2 predicate.
	(vec_set<V_256_512:mode): New expander.
	* config/i386/mmx.md (vec_setv2hi): Use vec_setm_sse41_operand
	as operand 2 predicate.

gcc/testsuite/

2021-07-12  Uroš Bizjak  <ubizjak@gmail.com>

	PR target/101424
	* gcc.target/i386/pr101424.c: New test.

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 986b758396a4356feba0f63eb5c723631186e8e2..0984f7cc44dc6ebda007b8c80dea733d75f10f09 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3604,7 +3604,7 @@
 (define_expand "vec_setv2hi"
   [(match_operand:V2HI 0 "register_operand")
    (match_operand:HI 1 "register_operand")
-   (match_operand 2 "vec_setm_operand")]
+   (match_operand 2 "vec_setm_sse41_operand")]
   "TARGET_SSE2"
 {
   if (CONST_INT_P (operands[2]))

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 9488632ce24a3ce234870e43814e47cc5afb4c7a..6aa1ea326270a1e0a318627016e4bc67c626e688 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1021,11 +1021,16 @@
 })
 
 ;; True for registers, or const_int_operand, used to vec_setm expander.
-(define_predicate "vec_setm_operand"
+(define_predicate "vec_setm_sse41_operand"
   (ior (and (match_operand 0 "register_operand")
            (match_test "TARGET_SSE4_1"))
        (match_code "const_int")))
 
+(define_predicate "vec_setm_avx2_operand"
+  (ior (and (match_operand 0 "register_operand")
+           (match_test "TARGET_AVX2"))
+       (match_code "const_int")))
+
 (define_predicate "vec_setm_mmx_operand"
   (ior (and (match_operand 0 "register_operand")
            (match_test "TARGET_SSE4_1")

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 17c9e571d5d7441b0201392b01dbcc62028d93d5..ab29999023dc25609f71c5d1bcb893a19849a3cd 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8486,9 +8486,9 @@
    (set_attr "mode" "DF")])
 
 (define_expand "vec_set<mode>"
-  [(match_operand:V 0 "register_operand")
+  [(match_operand:V_128 0 "register_operand")
    (match_operand:<ssescalarmode> 1 "register_operand")
-   (match_operand 2 "vec_setm_operand")]
+   (match_operand 2 "vec_setm_sse41_operand")]
   "TARGET_SSE"
 {
   if (CONST_INT_P (operands[2]))
@@ -8499,6 +8499,20 @@
   DONE;
 })
 
+(define_expand "vec_set<mode>"
+  [(match_operand:V_256_512 0 "register_operand")
+   (match_operand:<ssescalarmode> 1 "register_operand")
+   (match_operand 2 "vec_setm_avx2_operand")]
+  "TARGET_AVX"
+{
+  if (CONST_INT_P (operands[2]))
+    ix86_expand_vector_set (false, operands[0], operands[1],
+                           INTVAL (operands[2]));
+  else
+    ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
+  DONE;
+})
+
 (define_insn_and_split "*vec_extractv4sf_0"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=v,m,f,r")
        (vec_select:SF

diff --git a/gcc/testsuite/gcc.target/i386/pr101424.c b/gcc/testsuite/gcc.target/i386/pr101424.c
new file mode 100644 (file)
index 0000000..28bb723
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101424.c
@@ -0,0 +1,15 @@
+/* PR target/101424 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+typedef int v4df __attribute__((vector_size(32)));
+
+int foo_v4df_b, foo_v4df_c;
+
+v4df
+__attribute__foo_v4df ()
+{
+  v4df a;
+  a[foo_v4df_c] = foo_v4df_b;
+  return a;
+}