phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth

Due to its relatively low frequency, a noise stemming from the 24MHz PLL
reference clock may traverse the low-pass loop filter of ROPLL, which
could potentially generate some HDMI flash artifacts.

Reduce ROPLL loop bandwidth in an attempt to mitigate the problem.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index aee03e8655f66d4b25de39bd2b2bf49d7a8b5b86..8ba9b53c2309b22a496574b7731377049f50068f 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -500,9 +500,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
        REG_SEQ0(CMN_REG(0043), 0x00),
        REG_SEQ0(CMN_REG(0044), 0x46),
        REG_SEQ0(CMN_REG(0045), 0x24),
-       REG_SEQ0(CMN_REG(0046), 0xff),
        REG_SEQ0(CMN_REG(0047), 0x00),
-       REG_SEQ0(CMN_REG(0048), 0x44),
        REG_SEQ0(CMN_REG(0049), 0xfa),
        REG_SEQ0(CMN_REG(004a), 0x08),
        REG_SEQ0(CMN_REG(004b), 0x00),
@@ -575,6 +573,8 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
        REG_SEQ0(CMN_REG(0034), 0x00),
        REG_SEQ0(CMN_REG(003d), 0x40),
        REG_SEQ0(CMN_REG(0042), 0x78),
+       REG_SEQ0(CMN_REG(0046), 0xdd),
+       REG_SEQ0(CMN_REG(0048), 0x11),
        REG_SEQ0(CMN_REG(004e), 0x34),
        REG_SEQ0(CMN_REG(005c), 0x25),
        REG_SEQ0(CMN_REG(005e), 0x4f),