writel_relaxed(val, base + USB_USBMODE);
}
- if (phy->soc_config->has_hostpc)
- set_pts(phy, TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC);
- else
- set_pts(phy, 0);
+ set_pts(phy, phy->soc_config->uhsic_pts_value);
val = readl_relaxed(base + USB_TXFILLTUNING);
if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
.requires_pmc_ao_power_up = false,
.uhsic_registers_offset = 0,
.uhsic_tx_rtune = 0, /* 40 ohm */
+ .uhsic_pts_value = 0, /* UTMI */
};
static const struct tegra_phy_soc_config tegra30_soc_config = {
.requires_pmc_ao_power_up = true,
.uhsic_registers_offset = 0x400,
.uhsic_tx_rtune = 8, /* 50 ohm */
+ .uhsic_pts_value = TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC,
};
static const struct of_device_id tegra_usb_phy_id_table[] = {
* uhsic_registers_offset: for Tegra30+ where HSIC registers were offset
* comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2
* uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver
+ * uhsic_pts_value: parallel transceiver select enumeration value
*/
struct tegra_phy_soc_config {
bool requires_pmc_ao_power_up;
u32 uhsic_registers_offset;
u32 uhsic_tx_rtune;
+ u32 uhsic_pts_value;
};
struct tegra_utmip_config {