* mn10300_sim.h: Fix ordering of bits in the PSW.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index f3280ccd891a94459a86e376ab340f8e8b3f07bd..51efa7b80d715dd0a1e59265fc99d0e9b4462601 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,5 +1,7 @@
 Tue May  6 13:24:36 1997  Jeffrey A Law  (law@cygnus.com)
 
+       * mn10300_sim.h: Fix ordering of bits in the PSW.
+
        * interp.c: Improve hashing routine to avoid long list
        traversals for common instructions.  Add HASH_STAT support.
        Rewrite opcode dispatch code using a big switch instead of

diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index 2fcb85a78f5072c1697cb9fa15872c4084e75d81..40cef234bb40ae426c2c6d45ff6d4229c53ed4f0 100644 (file)
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -72,10 +72,10 @@ extern struct simops Simops[];
 #define PC     (State.regs[9])
 
 #define PSW (State.regs[11])
-#define PSW_V 0x1
-#define PSW_C 0x2
-#define PSW_N 0x4
-#define PSW_Z 0x8
+#define PSW_Z 0x1
+#define PSW_N 0x2
+#define PSW_C 0x4
+#define PSW_V 0x8
 
 #define REG_D0 0
 #define REG_A0 4