.list = fsl_sai_rates,
};
+static const char * const inc_mode[] = {
+ "On enabled and bitcount increment", "On enabled"
+};
+
+static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
+ FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
+static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
+ FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);
+
+static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = {
+ FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_SAI_TTCTL,
+ FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
+ fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
+ FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_SAI_TTCTL,
+ FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_SAI_TTCTL,
+ FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_SAI_TTCTN,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_SAI_TBCTN,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_SAI_TTCAP,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_SAI_RTCTL,
+ FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
+ fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
+ FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_SAI_RTCTL,
+ FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_SAI_RTCTL,
+ FSL_SAI_xTCTL_RBC_SHIFT, 1, 0,
+ fsl_asoc_get_volsw, fsl_asoc_put_volsw),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_SAI_RTCTN,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_SAI_RBCTN,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+ FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_SAI_RTCAP,
+ 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
+};
+
/**
* fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
*
return 0;
}
+static int fsl_sai_component_probe(struct snd_soc_component *component)
+{
+ struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
+
+ if (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN)
+ snd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls,
+ ARRAY_SIZE(fsl_sai_timestamp_ctrls));
+
+ return 0;
+}
+
static struct snd_soc_dai_driver fsl_sai_dai_template[] = {
{
.name = "sai-tx-rx",
static const struct snd_soc_component_driver fsl_component = {
.name = "fsl-sai",
+ .probe = fsl_sai_component_probe,
.resume = fsl_sai_dai_resume,
.legacy_dai_naming = 1,
};
case FSL_SAI_RDR5:
case FSL_SAI_RDR6:
case FSL_SAI_RDR7:
+ case FSL_SAI_TTCTN:
+ case FSL_SAI_RTCTN:
+ case FSL_SAI_TTCTL:
+ case FSL_SAI_TBCTN:
+ case FSL_SAI_TTCAP:
+ case FSL_SAI_RTCTL:
+ case FSL_SAI_RBCTN:
+ case FSL_SAI_RTCAP:
return true;
default:
return false;