/* Register SPDCR2 */
#define RSPI_SPDCR2_TTRG GENMASK(11, 8)
#define RSPI_SPDCR2_RTRG GENMASK(3, 0)
-#define RSPI_FIFO_SIZE 16
/* Register SPSR */
#define RSPI_SPSR_SPRF BIT(15)
#define RSPI_RESET_NUM 2
#define RSPI_CLK_NUM 3
+struct rzv2h_rspi_info {
+ unsigned int fifo_size;
+};
+
struct rzv2h_rspi_priv {
struct reset_control_bulk_data resets[RSPI_RESET_NUM];
struct spi_controller *controller;
+ const struct rzv2h_rspi_info *info;
void __iomem *base;
struct clk *tclk;
wait_queue_head_t wait;
writeb(0, rspi->base + RSPI_SSLP);
/* Setup FIFO thresholds */
- conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1);
+ conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1);
conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
writew(conf16, rspi->base + RSPI_SPDCR2);
rspi->controller = controller;
+ rspi->info = device_get_match_data(dev);
+
rspi->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rspi->base))
return PTR_ERR(rspi->base);
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
}
+static const struct rzv2h_rspi_info rzv2h_info = {
+ .fifo_size = 16,
+};
+
static const struct of_device_id rzv2h_rspi_match[] = {
- { .compatible = "renesas,r9a09g057-rspi" },
+ { .compatible = "renesas,r9a09g057-rspi", &rzv2h_info },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);