phy: rockchip: samsung-hdptx: Enable lane output in common helper

In preparation to support FRL mode, move the PHY lane output enablement
from the TMDS specific configuration to the common *_post_enable_lane()
helper and make sure it gets turned off in *_phy_disable().

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-5-8d5f97419c0b@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3c6eb6dbadd0913b7dd24a39f1da23576da7d389..33ebe63cdf1e7404d772505fe5057cb19a5bd645 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -797,6 +797,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
               HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
        regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
 
+       regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
+
        ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
                                       (val & HDPTX_O_PHY_RDY) &&
                                       (val & HDPTX_O_PLL_LOCK_DONE),
@@ -850,6 +852,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
        usleep_range(20, 30);
        reset_control_deassert(hdptx->rsts[RST_APB].rstc);
 
+       regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0);
        regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
        regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
        regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
@@ -1027,7 +1030,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
        }
 
        regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
-       regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
 
        rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
        rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);