clk: qcom: rpmh: Add support for Hawi RPMH clocks

Add RPMH clocks present in Qualcomm Hawi SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com>
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-4-530b538679f1@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 339a6bbcdc4c74c5fd949d7aa3ce85a711643889..8eae6fccc12700fa0cae3989c25f6b3218499734 100644 (file)
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -409,7 +409,9 @@ DEFINE_CLK_RPMH_VRM(clk5, _a2_e0, "C5A_E0", 2);
 DEFINE_CLK_RPMH_VRM(clk6, _a2_e0, "C6A_E0", 2);
 DEFINE_CLK_RPMH_VRM(clk7, _a2_e0, "C7A_E0", 2);
 DEFINE_CLK_RPMH_VRM(clk8, _a2_e0, "C8A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk9, _a2_e0, "C9A_E0", 2);
 
+DEFINE_CLK_RPMH_VRM(clk7, _a4_e0, "C7A_E0", 4);
 DEFINE_CLK_RPMH_VRM(clk11, _a4_e0, "C11A_E0", 4);
 
 DEFINE_CLK_RPMH_BCM(ce, "CE0");
@@ -984,6 +986,36 @@ static const struct clk_rpmh_desc clk_rpmh_nord = {
        .num_clks = ARRAY_SIZE(nord_rpmh_clocks),
 };
 
+static struct clk_hw *hawi_rpmh_clocks[] = {
+       [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
+       [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
+       [RPMH_DIV_CLK1]         = &clk_rpmh_clk11_a4_e0.hw,
+       [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2_e0.hw,
+       [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_e0_ao.hw,
+       [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a4_e0.hw,
+       [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a4_e0_ao.hw,
+       [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2_e0.hw,
+       [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_e0_ao.hw,
+       [RPMH_LN_BB_CLK4]       = &clk_rpmh_clk9_a2_e0.hw,
+       [RPMH_LN_BB_CLK4_A]     = &clk_rpmh_clk9_a2_e0_ao.hw,
+       [RPMH_RF_CLK1]          = &clk_rpmh_clk1_a1_e0.hw,
+       [RPMH_RF_CLK1_A]        = &clk_rpmh_clk1_a1_e0_ao.hw,
+       [RPMH_RF_CLK2]          = &clk_rpmh_clk2_a1_e0.hw,
+       [RPMH_RF_CLK2_A]        = &clk_rpmh_clk2_a1_e0_ao.hw,
+       [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a2_e0.hw,
+       [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a2_e0_ao.hw,
+       [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2_e0.hw,
+       [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a2_e0_ao.hw,
+       [RPMH_RF_CLK5]          = &clk_rpmh_clk5_a2_e0.hw,
+       [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_e0_ao.hw,
+       [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_hawi = {
+       .clks = hawi_rpmh_clocks,
+       .num_clks = ARRAY_SIZE(hawi_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
                                         void *data)
 {
@@ -1075,6 +1107,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
 static const struct of_device_id clk_rpmh_match_table[] = {
        { .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
        { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
+       { .compatible = "qcom,hawi-rpmh-clk", .data = &clk_rpmh_hawi},
        { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
        { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
        { .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},