arm64: dts: imx95-var-dart-sonata: add CAN controller

Add the MCP251xFD CAN controller connected to LPSPI7 chip select 1 on
the Sonata carrier board.

Add the second SPI chip select GPIO and describe the CAN interrupt and
pinctrl configuration.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts
index d2c7d83e1624a390a0d3f7b9ae198e1ad0d3c670..7a58ad38ffb4669a00d2502917f5765b10892100 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts
@@ -168,6 +168,10 @@
        status = "okay";
 };
 
+&gpio1 {
+       status = "okay";
+};
+
 &lpi2c3 {
        clock-frequency = <400000>;
        pinctrl-names = "default", "gpio", "sleep";
@@ -282,7 +286,8 @@
 &lpspi7 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpspi7>;
-       cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+       cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>,
+                  <&gpio1 7 GPIO_ACTIVE_LOW>;
        status = "okay";
 
        /* Resistive touch controller */
@@ -308,6 +313,19 @@
                ti,settle-delay-usec = /bits/ 16 <150>;
                ti,keep-vref-on;
        };
+
+       /* CAN controller */
+       can0: can@1 {
+               compatible = "microchip,mcp251xfd";
+               reg = <1>;
+               clocks = <&clk_osc_can0>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+               microchip,rx-int-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_can>;
+               spi-max-frequency = <12000000>;
+       };
 };
 
 /* Console */
@@ -444,6 +462,13 @@
                >;
        };
 
+       pinctrl_can: cangrp {
+               fsl,pins = <
+                       IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15                             0x31e
+                       IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22                             0x31e
+               >;
+       };
+
        pinctrl_captouch: captouchgrp {
                fsl,pins = <
                        IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13                             0x31e