riscv: dts: sophgo: reduce SG2042 MSI count to 16

The SG2042 MSI controller has one 32-bit doorbell register, and each bit
corresponds to an interrupt. At a glance, it seems that the MSI
controller can support 32 interrupts; however the PCI MSI capability
only supports 16-bit messages, which makes the high 16 interrupts
unusable in such way.

Reduce the MSI count to 16 to prevent producing MSI message values that
cannot fit 16-bit integers.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 3af77054974262b36901d6549120c8c50c6048c8..7eab0655f1500244d45be1b19fb0a5550f8cd89f 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -234,7 +234,7 @@
                        reg-names = "clr", "doorbell";
                        msi-controller;
                        #msi-cells = <0>;
-                       msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>;
+                       msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
                };
 
                rpgate: clock-controller@7030010368 {