Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 73181da607e7c993c9e1219952653cef95e8f973..e7a21588824762c51b71ebde95b567854f82decb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,74 @@
+2020-12-11  Dennis Zhang  <dennis.zhang@arm.com>
+
+       Backported from master:
+       2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry.
+       (vget_hi_half): Likewise.
+       * config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry.
+       (aarch64_vget_hi_halfv8bf): Likewise.
+       * config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic.
+       (vget_high_bf16): Likewise.
+
+2020-12-11  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+
+       Backported from master:
+       2020-11-03  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry.
+       (vbfcvt_high, bfcvt): Likewise.
+       * config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry.
+       (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise.
+       * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic.
+       * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise.
+       (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm_neon.h (vst2_lane_bf16, vst2q_lane_bf16)
+       (vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16)
+       (vst4q_lane_bf16): New intrinsics.
+       * config/arm/arm_neon_builtins.def: Touch it for:
+       __builtin_neon_vst2_lanev4bf, __builtin_neon_vst2_lanev8bf,
+       __builtin_neon_vst3_lanev4bf, __builtin_neon_vst3_lanev8bf,
+       __builtin_neon_vst4_lanev4bf,__builtin_neon_vst4_lanev8bf.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16)
+       (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16)
+       (vld4q_lane_bf16): Add intrinsics.
+       * config/arm/arm_neon_builtins.def: Touch for:
+       __builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf,
+       __builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf,
+       __builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf.
+       * config/arm/iterators.md (VQ_HS): Add V8BF to the iterator.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics.
+       * config/arm/arm_neon_builtins.def : Touch for:
+       __builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm-builtins.c (VAR14): Define macro.
+       * config/arm/arm_neon_builtins.def: Touch for:
+       __builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf.
+       * config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm_neon.h (vst1_lane_bf16, vst1q_lane_bf16): Add
+       intrinsics.
+       * config/arm/arm_neon_builtins.def (STORE1LANE): Add v4bf, v8bf.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf.
+       * config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add
+       intrinsics.
+
 2020-12-09  Kewen Lin  <linkw@linux.ibm.com>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9320aaa99a8856c917f7a790f069f86e319d5d41..77ef0ead5262935c6d73e0758eabd9d9d8ccb2ea 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201210
+20201211

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 3ea317a39dfffa36877d7afc822713a301f72996..9e20a208763eafc24bb0848c89f0a5ad1eabf130 100644 (file)
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,9 @@
+2020-12-10  Ed Schonberg  <schonberg@adacore.com>
+
+       PR ada/98230
+       * exp_attr.adb (Expand_N_Attribute_Reference, case Mod): Use base
+       type of argument to obtain static bound and required size.
+
 2020-12-08  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gcc-interface/trans.c (maybe_make_gnu_thunk): Return false if the

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 50b4fcbccce80e4b433f04f9383d132e5872beb7..0c497a8af174287236535f032bd875136b15b85f 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,13 @@
+2020-12-10  Patrick Palka  <ppalka@redhat.com>
+
+       Backported from master:
+       2020-07-30  Patrick Palka  <ppalka@redhat.com>
+
+       PR c++/64194
+       * pt.c (resolve_overloaded_unification): If the function
+       template specialization has a placeholder return type,
+       then instantiate it before attempting unification.
+
 2020-12-09  Jason Merrill  <jason@redhat.com>
 
        PR c++/93083

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0ae4cf6b9438829ab363646057753f373235f165..ae8560a479c971310b334ccc38e709193673245f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,83 @@
+2020-12-11  Dennis Zhang  <dennis.zhang@arm.com>
+
+       Backported from master:
+       2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
+
+       * gcc.target/aarch64/advsimd-intrinsics/bf16_get.c: New test.
+
+2020-12-11  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+
+       Backported from master:
+       2020-11-03  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+
+       * gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
+       (test_vcvt_f32_bf16, test_vcvtq_low_f32_bf16): New tests.
+       (test_vcvtq_high_f32_bf16, test_vcvth_f32_bf16): Likewise.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_bf16_indices_1.c:
+       Run it also for arm-*-*.
+       * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/arm/simd/vstn_lane_bf16_1.c: New test.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c:
+       Run it also for the arm backend.
+       * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c:
+       Likewise.
+       * gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/simd/vst1_bf16_1.c: New test.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/simd/vld1_bf16_1.c: New test.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/simd/vst1_lane_bf16_1.c: New testcase.
+       * gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
+       * gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
+
+2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/simd/vld1_lane_bf16_1.c: New testcase.
+       * gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
+       * gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
+
+2020-12-10  Ed Schonberg  <schonberg@adacore.com>
+
+       * gnat.dg/modular6.adb: New test.
+
+2020-12-10  Patrick Palka  <ppalka@redhat.com>
+
+       Backported from master:
+       2020-07-30  Patrick Palka  <ppalka@redhat.com>
+
+       PR c++/64194
+       * g++.dg/cpp1y/auto-fn60.C: New test.
+
 2020-12-09  Jason Merrill  <jason@redhat.com>
 
        PR c++/93083