drm/amd/display: Don't disable dtb as dto src during dpms off

[WHY & HOW]
Adjusting otg dto programming in this path is unsafe otg may be en at
this time, swapping its src sel for example was discovered to cause
visual artifacts and was moved to dcn31_program_pix_clk (where otg is
guaranteed off) but dto functional clk enable bit is not cleared.

dcn31_program_pix_clk is called during dpms on, so until that point
we will have a otg with functional src sel set (Sel DTBclk) and that
functional clk dto en is unset (i.e DTB DTO EN), which is invalid and tg
will not function and system will hang on something such as flip
incoming from OS during dpms off. will scope out dcn315 as it was
affecting diags tests on certain CI machines (not crbs)

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Ausef Yousof <Ausef.Yousof@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index e8730cc40edbe865e60cbb59d65e2942d66c124a..a9a3001109c35efe38df9ef8ef0a58bbd6134b13 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1186,8 +1186,10 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
                if (dccg) {
                        dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
                        dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
-                       if (dccg && dccg->funcs->set_dtbclk_dto)
-                               dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+                       if (dc->ctx->dce_version == DCN_VERSION_3_15) {
+                               if (dccg && dccg->funcs->set_dtbclk_dto)
+                                       dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+                       }
                }
        } else if (dccg && dccg->funcs->disable_symclk_se) {
                dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 486f7b723ceb1c6311ca6e3c12fa0d5f208e13a9..bc06b7b3d67d905aac31fd35c4b5488dcb2336af 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2808,6 +2808,8 @@ void dcn20_reset_back_end_for_pipe(
 {
        struct dc_link *link = pipe_ctx->stream->link;
        const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
+       struct dccg *dccg = dc->res_pool->dccg;
+       struct dtbclk_dto_params dto_params = {0};
 
        DC_LOGGER_INIT(dc->ctx->logger);
        if (pipe_ctx->stream_res.stream_enc == NULL) {
@@ -2868,6 +2870,13 @@ void dcn20_reset_back_end_for_pipe(
                                        &pipe_ctx->link_res, pipe_ctx->stream->signal);
                        link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
                }
+               if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg
+                       && dc->ctx->dce_version != DCN_VERSION_3_15) {
+                       dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
+                       dto_params.timing = &pipe_ctx->stream->timing;
+                       if (dccg && dccg->funcs->set_dtbclk_dto)
+                               dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+               }
        }
 
 /*