vector.md (vec_unpacks_hi_v4sf): Correct for endianness.

2013-10-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for
	endianness.
	(vec_unpacks_lo_v4sf): Likewise.
	(vec_unpacks_float_hi_v4si): Likewise.
	(vec_unpacks_float_lo_v4si): Likewise.
	(vec_unpacku_float_hi_v4si): Likewise.
	(vec_unpacku_float_lo_v4si): Likewise.

From-SVN: r203714

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index be6345c8447ca64f455ac8279510f250281d7d6b..5638730158b8dafcdd8ef4977e896415c61309d6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-10-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for
+       endianness.
+       (vec_unpacks_lo_v4sf): Likewise.
+       (vec_unpacks_float_hi_v4si): Likewise.
+       (vec_unpacks_float_lo_v4si): Likewise.
+       (vec_unpacku_float_hi_v4si): Likewise.
+       (vec_unpacku_float_lo_v4si): Likewise.
+
 2013-10-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
        * config/rs6000/vsx.md (vsx_concat_<mode>): Adjust output for LE.

diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index e88d879591e3e27b755dfc002fb17673444c384c..8b067b19729961fed0f4714def8252b79fa1005e 100644 (file)
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -872,7 +872,7 @@
 {
   rtx reg = gen_reg_rtx (V4SFmode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], true);
+  rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
   DONE;
 })
@@ -884,7 +884,7 @@
 {
   rtx reg = gen_reg_rtx (V4SFmode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], false);
+  rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
   DONE;
 })
@@ -896,7 +896,7 @@
 {
   rtx reg = gen_reg_rtx (V4SImode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], true);
+  rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
   DONE;
 })
@@ -908,7 +908,7 @@
 {
   rtx reg = gen_reg_rtx (V4SImode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], false);
+  rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
   DONE;
 })
@@ -920,7 +920,7 @@
 {
   rtx reg = gen_reg_rtx (V4SImode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], true);
+  rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
   DONE;
 })
@@ -932,7 +932,7 @@
 {
   rtx reg = gen_reg_rtx (V4SImode);
 
-  rs6000_expand_interleave (reg, operands[1], operands[1], false);
+  rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
   DONE;
 })