Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 01523448590d17ac081e47c607411b8e6b2808ba..7bee68240af7639c1db9abcef908eef6438b764a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2021-05-24  Alex Coplan  <alex.coplan@arm.com>
+
+       Backported from master:
+       2021-05-10  Alex Coplan  <alex.coplan@arm.com>
+
+       PR target/99960
+       * config/arm/mve.md (*mve_mov<mode>): Simplify output code. Use
+       vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores.
+
 2021-05-20  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e2a9538cdbdad020b48c76ae467fbf0823f874d0..e64bfabbbe33e50c671849bffc8ca547ba9a5f77 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20210524
+20210525

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 60c48fb4c2f8644afc1ca344f973898c8c4403de..656c219446f71611ad5ffac0f9264ab1c5850492 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,22 @@
+2021-05-24  Alex Coplan  <alex.coplan@arm.com>
+
+       Backported from master:
+       2021-05-10  Alex Coplan  <alex.coplan@arm.com>
+
+       PR target/99960
+       * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c:
+       Update now that we're (correctly) using full 128-bit vector
+       loads/stores.
+       * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c:
+       Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c:
+       Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c:
+       Likewise.
+       * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c:
+       Likewise.
+
 2021-05-21  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gnat.dg/derived_type7.adb, gnat.dg/derived_type7.ads: New test.