arm64: dts: qcom: msm8939: Fix CPU node "enable-method" property dependencies

The "spin-table" enable-method requires "cpu-release-addr" property,
so add a dummy entry. It is assumed the bootloader will fill in the
correct values.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-5-63d7dc9ddd0a@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index 5e8c3ac39de8b1f974a7e1499c7c805f21735569..ca478db63be4578b92d85e178548c5e16b29bf03 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -47,6 +47,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x100>;
                        next-level-cache = <&l2_1>;
                        qcom,acc = <&acc0>;
@@ -65,6 +66,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x101>;
                        next-level-cache = <&l2_1>;
                        qcom,acc = <&acc1>;
@@ -78,6 +80,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x102>;
                        next-level-cache = <&l2_1>;
                        qcom,acc = <&acc2>;
@@ -91,6 +94,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x103>;
                        next-level-cache = <&l2_1>;
                        qcom,acc = <&acc3>;
@@ -104,6 +108,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x0>;
                        qcom,acc = <&acc4>;
                        qcom,saw = <&saw4>;
@@ -122,6 +127,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x1>;
                        next-level-cache = <&l2_0>;
                        qcom,acc = <&acc5>;
@@ -135,6 +141,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x2>;
                        next-level-cache = <&l2_0>;
                        qcom,acc = <&acc6>;
@@ -148,6 +155,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "spin-table";
+                       cpu-release-addr = /bits/ 64 <0>;
                        reg = <0x3>;
                        next-level-cache = <&l2_0>;
                        qcom,acc = <&acc7>;