drm/msm/dsi: Print dual-DSI-adjusted pclk instead of original mode pclk

[ Upstream commit f12e0e12524a34bf145f7b80122e653ffe3d130a ]

When dual-DSI (bonded DSI) was added in commit ed9976a09b48
("drm/msm/dsi: adjust dsi timing for dual dsi mode") some DBG() prints
were not updated, leading to print the original mode->clock rather
than the adjusted (typically the mode clock divided by two, though more
recently also adjusted for DSC compression) msm_host->pixel_clk_rate
which is passed to clk_set_rate() just below.  Fix that by printing the
actual pixel_clk_rate that is being set.

Fixes: ed9976a09b48 ("drm/msm/dsi: adjust dsi timing for dual dsi mode")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/589896/
Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-1-78ae3ee9a697@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 8d0612caf6c21b62116c3ce3f38f9dd33c11f507..c563ecf6e7b94d29384e799d7d7d7d4fb833b264 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -501,8 +501,8 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
        unsigned long byte_intf_rate;
        int ret;
 
-       DBG("Set clk rates: pclk=%d, byteclk=%lu",
-               msm_host->mode->clock, msm_host->byte_clk_rate);
+       DBG("Set clk rates: pclk=%lu, byteclk=%lu",
+           msm_host->pixel_clk_rate, msm_host->byte_clk_rate);
 
        ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
                                  msm_host->byte_clk_rate);
@@ -583,9 +583,9 @@ int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
 {
        int ret;
 
-       DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
-               msm_host->mode->clock, msm_host->byte_clk_rate,
-               msm_host->esc_clk_rate, msm_host->src_clk_rate);
+       DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
+           msm_host->pixel_clk_rate, msm_host->byte_clk_rate,
+           msm_host->esc_clk_rate, msm_host->src_clk_rate);
 
        ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
        if (ret) {