]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
sunxi: clock: H6: factor out H6/H616 CPU clock setup
authorAndre Przywara <andre.przywara@arm.com>
Sat, 25 Jan 2025 13:40:05 +0000 (13:40 +0000)
committerAndre Przywara <andre.przywara@arm.com>
Sun, 27 Jul 2025 21:57:35 +0000 (22:57 +0100)
When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.

The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
arch/arm/mach-sunxi/clock_sun50i_h6.c

index 90436b45b40ef1f94788f6baa2d4a0dfcad4c85c..84064c4ed86a2ba453a718bbdaa886b3bda7f857 100644 (file)
@@ -120,29 +120,37 @@ static void clock_set_pll(u32 *reg, unsigned int n)
        }
 }
 
-void clock_set_pll1(unsigned int clk)
+static void clock_h6_set_cpu_pll(unsigned int n_factor)
 {
        void *const ccm = (void *)SUNXI_CCM_BASE;
        u32 val;
 
-       /* Do not support clocks < 288MHz as they need factor P */
-       if (clk < 288000000) clk = 288000000;
-
-       /* Switch to 24MHz clock while changing PLL1 */
+       /* Switch CPU clock source to 24MHz HOSC while changing the PLL */
        val = readl(ccm + CCU_H6_CPU_AXI_CFG);
        val &= ~CCM_CPU_AXI_MUX_MASK;
        val |= CCM_CPU_AXI_MUX_OSC24M;
        writel(val, ccm + CCU_H6_CPU_AXI_CFG);
 
-       clock_set_pll(ccm + CCU_H6_PLL1_CFG, clk / 24000000);
+       clock_set_pll(ccm + CCU_H6_PLL1_CFG, n_factor);
 
-       /* Switch CPU to PLL1 */
+       /* Switch CPU clock source to the CPU PLL */
        val = readl(ccm + CCU_H6_CPU_AXI_CFG);
        val &= ~CCM_CPU_AXI_MUX_MASK;
        val |= CCM_CPU_AXI_MUX_PLL_CPUX;
        writel(val, ccm + CCU_H6_CPU_AXI_CFG);
 }
 
+void clock_set_pll1(unsigned int clk)
+{
+       /* Do not support clocks < 288MHz as they need factor P */
+       if (clk < 288000000)
+               clk = 288000000;
+
+       clk /= 24000000;
+
+       clock_h6_set_cpu_pll(clk);
+}
+
 int clock_twi_onoff(int port, int state)
 {
        void *const ccm = (void *)SUNXI_CCM_BASE;