arm64: dts: imx95: add edma[1..3] nodes

Add eDMA1, eDMA2 and eDMA3 support for iMX95.
Add dmas and dma-names for each peripheral, which use eDMA.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 086885f42b50643e210582675e78bae771d2c249..58c4945871d0cc70357b1488f48aa6b5e6709294 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -3,6 +3,7 @@
  * Copyright 2024 NXP
  */
 
+#include <dt-bindings/dma/fsl-edma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -405,6 +406,152 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       edma2: dma-controller@42000000 {
+                               compatible = "fsl,imx95-edma5";
+                               reg = <0x42000000 0x210000>;
+                               #dma-cells = <3>;
+                               dma-channels = <64>;
+                               interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+                               clock-names = "dma";
+                       };
+
+                       edma3: dma-controller@42210000 {
+                               compatible = "fsl,imx95-edma5";
+                               reg = <0x42210000 0x210000>;
+                               #dma-cells = <3>;
+                               dma-channels = <64>;
+                               interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+                               clock-names = "dma";
+                       };
+
                        mu7: mailbox@42430000 {
                                compatible = "fsl,imx95-mu";
                                reg = <0x42430000 0x10000>;
@@ -464,6 +611,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -476,6 +625,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -488,6 +639,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI3>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -500,6 +653,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI4>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -510,6 +665,8 @@
                                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART3>;
                                clock-names = "ipg";
+                               dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -520,6 +677,8 @@
                                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART4>;
                                clock-names = "ipg";
+                               dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -530,6 +689,8 @@
                                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART5>;
                                clock-names = "ipg";
+                               dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -540,6 +701,8 @@
                                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART6>;
                                clock-names = "ipg";
+                               dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -550,6 +713,8 @@
                                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART7>;
                                clock-names = "ipg";
+                               dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -560,6 +725,8 @@
                                interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART8>;
                                clock-names = "ipg";
+                               dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -572,6 +739,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -584,6 +753,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -596,6 +767,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -608,6 +781,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -620,6 +795,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI5>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -632,6 +809,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI6>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -644,6 +823,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI7>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -656,6 +837,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI8>,
                                         <&scmi_clk IMX95_CLK_BUSWAKEUP>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -796,6 +979,46 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       edma1: dma-controller@44000000 {
+                               compatible = "fsl,imx93-edma3";
+                               reg = <0x44000000 0x200000>;
+                               #dma-cells = <3>;
+                               dma-channels = <31>;
+                               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+                               clock-names = "dma";
+                       };
+
                        mu1: mailbox@44220000 {
                                compatible = "fsl,imx95-mu";
                                reg = <0x44220000 0x10000>;
@@ -830,6 +1053,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -842,6 +1067,8 @@
                                clock-names = "per", "ipg";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -854,6 +1081,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI1>,
                                         <&scmi_clk IMX95_CLK_BUSAON>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -866,6 +1095,8 @@
                                clocks = <&scmi_clk IMX95_CLK_LPSPI2>,
                                         <&scmi_clk IMX95_CLK_BUSAON>;
                                clock-names = "per", "ipg";
+                               dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
@@ -876,6 +1107,8 @@
                                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART1>;
                                clock-names = "ipg";
+                               dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -886,6 +1119,8 @@
                                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&scmi_clk IMX95_CLK_LPUART2>;
                                clock-names = "ipg";
+                               dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };