reg = <0x0 0x1fa20000 0x0 0x388>;
};
- syscon@1fbe3400 {
+ pbus_csr: syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+ mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+ mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001
-Message-ID: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed, 8 Jan 2025 10:50:40 +0100
Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in
From e4c7dfd953f7618f0ccb70d87c1629634f306fab Mon Sep 17 00:00:00 2001
-Message-ID: <e4c7dfd953f7618f0ccb70d87c1629634f306fab.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed, 8 Jan 2025 10:50:41 +0100
Subject: [PATCH 2/6] PCI: mediatek-gen3: Move reset/assert callbacks in
From 0c9d2d2ef0d916b490a9222ed20ff4616fca876d Mon Sep 17 00:00:00 2001
-Message-ID: <0c9d2d2ef0d916b490a9222ed20ff4616fca876d.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed, 8 Jan 2025 10:50:42 +0100
Subject: [PATCH 3/6] PCI: mediatek-gen3: Add comment about initialization
From 90d4e466c9ea2010f33880a36317a8486ccbe082 Mon Sep 17 00:00:00 2001
-Message-ID: <90d4e466c9ea2010f33880a36317a8486ccbe082.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed, 8 Jan 2025 10:50:43 +0100
Subject: [PATCH 4/6] PCI: mediatek-gen3: Move reset delay in
From c98bee18d0a094e37100c85effe5e161418f8644 Mon Sep 17 00:00:00 2001
-Message-ID: <c98bee18d0a094e37100c85effe5e161418f8644.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed, 8 Jan 2025 10:50:44 +0100
Subject: [PATCH 5/6] PCI: mediatek-gen3: Rely on msleep() in
From 491cb9c5084790aafa02e843349492c284373231 Mon Sep 17 00:00:00 2001
-Message-ID: <491cb9c5084790aafa02e843349492c284373231.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Thu, 9 Jan 2025 00:30:45 +0100
Subject: [PATCH 6/6] PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for
--- /dev/null
+From b6d7bb0d3bd74b491e2e6fd59c4d5110d06fd63b Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sat, 1 Feb 2025 12:00:18 +0100
+Subject: [PATCH] PCI: mediatek-gen3: Remove leftover mac_reset assert for
+ Airoha EN7581 SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove a leftover assert for mac_reset line in mtk_pcie_en7581_power_up().
+
+This is not harmful since EN7581 does not requires mac_reset and
+mac_reset is not defined in EN7581 device tree.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Link: https://lore.kernel.org/r/20250201-pcie-en7581-remove-mac_reset-v2-1-a06786cdc683@kernel.org
+[kwilczynski: commit log]
+Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -902,7 +902,6 @@ static int mtk_pcie_en7581_power_up(stru
+ */
+ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
+ pcie->phy_resets);
+- reset_control_assert(pcie->mac_reset);
+
+ /* Wait for the time needed to complete the reset lines assert. */
+ msleep(PCIE_EN7581_RESET_TIME_MS);
--- /dev/null
+From 249b78298078448a699c39356d27d8183af4b281 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Feb 2025 09:04:07 +0100
+Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
+ SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Configure PBus base address and address mask to allow the hw
+to detect if a given address is accessible on PCIe controller.
+
+Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support")
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/20250225-en7581-pcie-pbus-csr-v4-2-24324382424a@kernel.org
+Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -15,6 +15,7 @@
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_device.h>
+@@ -24,6 +25,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regmap.h>
+ #include <linux/reset.h>
+
+ #include "../pci.h"
+@@ -892,9 +894,13 @@ static int mtk_pcie_parse_port(struct mt
+
+ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
+ {
++ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct device *dev = pcie->dev;
++ struct resource_entry *entry;
++ struct regmap *pbus_regmap;
++ u32 val, args[2], size;
++ resource_size_t addr;
+ int err;
+- u32 val;
+
+ /*
+ * The controller may have been left out of reset by the bootloader
+@@ -907,6 +913,26 @@ static int mtk_pcie_en7581_power_up(stru
+ msleep(PCIE_EN7581_RESET_TIME_MS);
+
+ /*
++ * Configure PBus base address and base address mask to allow the
++ * hw to detect if a given address is accessible on PCIe controller.
++ */
++ pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
++ "mediatek,pbus-csr",
++ ARRAY_SIZE(args),
++ args);
++ if (IS_ERR(pbus_regmap))
++ return PTR_ERR(pbus_regmap);
++
++ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
++ if (!entry)
++ return -ENODEV;
++
++ addr = entry->res->start - entry->offset;
++ regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
++ size = lower_32_bits(resource_size(entry->res));
++ regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
++
++ /*
+ * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
+ * requires PHY initialization and power-on before PHY reset deassert.
+ */
+++ /dev/null
-From ca4217f3117dceb2d01e179d02031a8758404624 Mon Sep 17 00:00:00 2001
-Message-ID: <ca4217f3117dceb2d01e179d02031a8758404624.1736961235.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 3 Sep 2024 23:14:02 +0200
-Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
- SoC
-
-Configure PBus base address and address mask in order to allow the hw
-detecting if a given address is on PCIE0, PCIE1 or PCIE2.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++-
- 1 file changed, 28 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -15,6 +15,7 @@
- #include <linux/irqchip/chained_irq.h>
- #include <linux/irqdomain.h>
- #include <linux/kernel.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/msi.h>
- #include <linux/of_device.h>
-@@ -24,6 +25,7 @@
- #include <linux/platform_device.h>
- #include <linux/pm_domain.h>
- #include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
- #include <linux/reset.h>
-
- #include "../pci.h"
-@@ -122,6 +124,13 @@
-
- #define PCIE_MTK_RESET_TIME_US 10
-
-+#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3))
-+#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3))
-+#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \
-+ ((_n) == 2 ? 0x28000000 : \
-+ (_n) == 1 ? 0x24000000 : 0x20000000)
-+#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26)
-+
- /* Time in ms needed to complete PCIe reset on EN7581 SoC */
- #define PCIE_EN7581_RESET_TIME_MS 100
-
-@@ -893,7 +902,8 @@ static int mtk_pcie_parse_port(struct mt
- static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
- {
- struct device *dev = pcie->dev;
-- int err;
-+ struct regmap *map;
-+ int err, slot;
- u32 val;
-
- /*
-@@ -907,6 +917,23 @@ static int mtk_pcie_en7581_power_up(stru
- /* Wait for the time needed to complete the reset lines assert. */
- msleep(PCIE_EN7581_RESET_TIME_MS);
-
-+ map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
-+ if (IS_ERR(map))
-+ return PTR_ERR(map);
-+
-+ /*
-+ * Configure PBus base address and address mask in order to allow the
-+ * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2.
-+ */
-+ slot = of_get_pci_domain_nr(dev->of_node);
-+ if (slot < 0)
-+ return slot;
-+
-+ regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot),
-+ PCIE_EN7581_PBUS_BASE_ADDR(slot));
-+ regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot),
-+ PCIE_EN7581_PBUS_BASE_ADDR_MASK);
-+
- /*
- * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
- * requires PHY initialization and power-on before PHY reset deassert.
+++ /dev/null
-From c4defe43ce17a87e6341d126ba736d9f7ebdc541 Mon Sep 17 00:00:00 2001
-Message-ID: <c4defe43ce17a87e6341d126ba736d9f7ebdc541.1736962769.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Wed, 15 Jan 2025 18:36:26 +0100
-Subject: [PATCH] PCI: mediatek-gen3: Remove mac_reset assert leftover for
- Airoha EN7581 SoC.
-
-Remove a leftover assert for mac_reset line in mtk_pcie_en7581_power_up().
-This is not armful since EN7581 does not requires mac_reset and
-mac_reset is not defined in EN7581 device tree.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -912,7 +912,6 @@ static int mtk_pcie_en7581_power_up(stru
- */
- reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
- pcie->phy_resets);
-- reset_control_assert(pcie->mac_reset);
-
- /* Wait for the time needed to complete the reset lines assert. */
- msleep(PCIE_EN7581_RESET_TIME_MS);
projects / thirdparty / openwrt.git / commitdiff
