fbnic: Set Relaxed Ordering PCIe TLP attributes for DMA engines

Add ATTR CSR bit field definitions for the DMA engine TLP header
configuration registers:
  AW_CFG: RDE_ATTR[17:15], RQM_ATTR[14:12], TQM_ATTR[11:9]
  AR_CFG: TDE_ATTR[17:15], RQM_ATTR[14:12], TQM_ATTR[11:9]

These fields control the PCIe TLP attribute bits for outbound
transactions from the TQM, RQM, RDE (write path), and TDE (read path)
DMA engines. An enum is added with standard PCIe TLP attribute values:
NS (No Snoop), RO (Relaxed Ordering), and IDO (ID-based Ordering).

Read the PCIe Relaxed Ordering capability at probe time and store it in
fbnic_dev. Configure Relaxed Ordering on the PCIe TLP attributes in
fbnic_mbx_init_desc_ring when the capability is enabled. For the write
path (AW_CFG), set RO on RDE and TQM attributes. For the read path
(AR_CFG), set RO on all three attributes (TDE, RQM, TQM). This allows
the PCIe fabric to reorder these transactions for improved throughput.

Signed-off-by: Alexander Duyck <alexanderduyck@fb.com>
Signed-off-by: Dimitri Daskalakis <daskald@meta.com>
Link: https://patch.msgid.link/20260327204445.3074446-1-dimitri.daskalakis1@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/meta/fbnic/fbnic.h b/drivers/net/ethernet/meta/fbnic/fbnic.h
index f7df5302e91a3f4d0b44ccb7d3387e2a95606311..d0715695c43e751ca73b41c9aa75280dcac7853b 100644 (file)
--- a/drivers/net/ethernet/meta/fbnic/fbnic.h
+++ b/drivers/net/ethernet/meta/fbnic/fbnic.h
@@ -57,6 +57,7 @@ struct fbnic_dev {
        u64 dsn;
        u32 mps;
        u32 readrq;
+       u8 relaxed_ord;
 
        /* Local copy of the devices TCAM */
        struct fbnic_act_tcam act_tcam[FBNIC_RPC_TCAM_ACT_NUM_ENTRIES];

diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_csr.h b/drivers/net/ethernet/meta/fbnic/fbnic_csr.h
index 43de522af17271f819603ae81db0be1e0b91912b..81794bd326e160713c7a7b4d80cfad3c0fdac995 100644 (file)
--- a/drivers/net/ethernet/meta/fbnic/fbnic_csr.h
+++ b/drivers/net/ethernet/meta/fbnic/fbnic_csr.h
@@ -975,9 +975,21 @@ enum {
 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG    0x3103d         /* 0xc40f4 */
 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH      CSR_BIT(19)
 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME                CSR_BIT(18)
+#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RDE_ATTR   CSR_GENMASK(17, 15)
+#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RQM_ATTR   CSR_GENMASK(14, 12)
+#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_TQM_ATTR   CSR_GENMASK(11, 9)
+enum {
+       FBNIC_TLP_ATTR_NS       = 1,
+       FBNIC_TLP_ATTR_RO       = 2,
+       FBNIC_TLP_ATTR_IDO      = 4,
+};
+
 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG    0x3103e         /* 0xc40f8 */
 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_FLUSH      CSR_BIT(19)
 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME                CSR_BIT(18)
+#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TDE_ATTR   CSR_GENMASK(17, 15)
+#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_RQM_ATTR   CSR_GENMASK(14, 12)
+#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TQM_ATTR   CSR_GENMASK(11, 9)
 #define FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0 \
                                        0x3106e         /* 0xc41b8 */
 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0 \

diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_devlink.c b/drivers/net/ethernet/meta/fbnic/fbnic_devlink.c
index f1c992f5fe94621902154be70b8aae24954b4003..546e1c12d287c72f71e70b9a5560fe3ac603fcab 100644 (file)
--- a/drivers/net/ethernet/meta/fbnic/fbnic_devlink.c
+++ b/drivers/net/ethernet/meta/fbnic/fbnic_devlink.c
@@ -647,6 +647,7 @@ struct fbnic_dev *fbnic_devlink_alloc(struct pci_dev *pdev)
        fbd->dsn = pci_get_dsn(pdev);
        fbd->mps = pcie_get_mps(pdev);
        fbd->readrq = pcie_get_readrq(pdev);
+       fbd->relaxed_ord = pcie_relaxed_ordering_enabled(pdev);
 
        fbd->mac_addr_boundary = FBNIC_RPC_TCAM_MACDA_DEFAULT_BOUNDARY;
 

diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_fw.c b/drivers/net/ethernet/meta/fbnic/fbnic_fw.c
index c2bad51bdde60b32308dfbf64ec32c6f35869767..0c6812fcf185153ac66f2089214f87cf8dd499e6 100644 (file)
--- a/drivers/net/ethernet/meta/fbnic/fbnic_fw.c
+++ b/drivers/net/ethernet/meta/fbnic/fbnic_fw.c
@@ -448,6 +448,7 @@ static int fbnic_fw_xmit_simple_msg(struct fbnic_dev *fbd, u32 msg_type)
 
 static int fbnic_mbx_init_desc_ring(struct fbnic_dev *fbd, int mbx_idx)
 {
+       u8 tlp_attr = fbd->relaxed_ord ? FBNIC_TLP_ATTR_RO : 0;
        struct fbnic_fw_mbx *mbx = &fbd->mbx[mbx_idx];
 
        mbx->ready = true;
@@ -456,14 +457,24 @@ static int fbnic_mbx_init_desc_ring(struct fbnic_dev *fbd, int mbx_idx)
        case FBNIC_IPC_MBX_RX_IDX:
                /* Enable DMA writes from the device */
                wr32(fbd, FBNIC_PUL_OB_TLP_HDR_AW_CFG,
-                    FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME);
+                    FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME |
+                    FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AW_CFG_RDE_ATTR,
+                               tlp_attr) |
+                    FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AW_CFG_TQM_ATTR,
+                               tlp_attr));
 
                /* Make sure we have a page for the FW to write to */
                return fbnic_mbx_alloc_rx_msgs(fbd);
        case FBNIC_IPC_MBX_TX_IDX:
                /* Enable DMA reads from the device */
                wr32(fbd, FBNIC_PUL_OB_TLP_HDR_AR_CFG,
-                    FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME);
+                    FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME |
+                    FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_TDE_ATTR,
+                               tlp_attr) |
+                    FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_RQM_ATTR,
+                               tlp_attr) |
+                    FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_TQM_ATTR,
+                               tlp_attr));
                break;
        }