&& i.imm_operands && i.operands > i.imm_operands))
swap_2_operands (0, 1);
- if (i.imm_operands)
+ /* All legitimate immediates are placed first now. Others, if any, will be
+ rejected by match_template() anyway. */
+ if (operand_type_check (i.types[0], imm))
{
/* For USER_MSR and MSR_IMM instructions, imm32 stands for the name of a
model specific register (MSR). That's an unsigned quantity, whereas all
if (is_cpu(current_templates.start, CpuUSER_MSR)
|| t->mnem_off == MN_rdmsr
|| t->mnem_off == MN_wrmsrns)
- {
- for (j = 0; j < i.imm_operands; j++)
- i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
- }
+ i.types[0] = smallest_imm_type (i.op[0].imms->X_add_number);
else
optimize_imm ();
}
&& current_templates.start->mnem_off != MN_jmpabs))
guess_suffix = LONG_MNEM_SUFFIX;
- for (op = i.operands; --op >= 0;)
+ for (op = i.imm_operands; --op >= 0;)
if (operand_type_check (i.types[op], imm))
{
switch (i.op[op].imms->X_op)
.* Assembler messages:
.*:5: Error: operand type mismatch for `rdmsr'
.*:6: Error: operand type mismatch for `rdmsr'
-.*:7: Error: operand type mismatch for `wrmsrns'
+.*:7: Error: operand type mismatch for `rdmsr'
.*:8: Error: operand type mismatch for `wrmsrns'
+.*:9: Error: operand type mismatch for `wrmsrns'
+.*:10: Error: operand type mismatch for `wrmsrns'
.*:6: Error: operand type mismatch for `urdmsr'
.*:7: Error: operand type mismatch for `urdmsr'
.*:8: Error: operand type mismatch for `urdmsr'
-.*:9: Error: operand type mismatch for `uwrmsr'
+.*:9: Error: operand type mismatch for `urdmsr'
.*:10: Error: operand type mismatch for `uwrmsr'
.*:11: Error: operand type mismatch for `uwrmsr'
.*:12: Error: operand type mismatch for `uwrmsr'
+.*:13: Error: operand type mismatch for `uwrmsr'
+.*:14: Error: operand type mismatch for `uwrmsr'
urdmsr $-32767, %r14
urdmsr $-2147483648, %r14
urdmsr $0x7fffffffffffffff, %r14
+ urdmsr (%rax), $0
uwrmsr %r12, $-1
uwrmsr %r12, $-32767
uwrmsr %r12, $-2147483648
uwrmsr %r12, $0x7fffffffffffffff
+ uwrmsr $0, (%rax)