]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: setup: name 'tcr2' register
authorYicong Yang <yangyicong@hisilicon.com>
Sat, 2 Nov 2024 10:42:32 +0000 (18:42 +0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 5 Nov 2024 10:55:55 +0000 (10:55 +0000)
TCR2_EL1 introduced some additional controls besides TCR_EL1. Currently
only PIE is supported and enabled by writing TCR2_EL1 directly if PIE
detected.

Introduce a named register 'tcr2' just like 'tcr' we've already had.
It'll be initialized to 0 and updated if certain feature detected and
needs to be enabled. Touch the TCR2_EL1 registers at last with the
updated 'tcr2' value if FEAT_TCR2 supported by checking
ID_AA64MMFR3_EL1.TCRX. Then we can extend the support of other features
controlled by TCR2_EL1.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20241102104235.62560-3-yangyicong@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/mm/proc.S

index 8abdc7fed3210d03c2d7fc99b7708d627e8228be..ccbae4525891e386aab90c030d7d716b80ccd21f 100644 (file)
@@ -465,10 +465,12 @@ SYM_FUNC_START(__cpu_setup)
         */
        mair    .req    x17
        tcr     .req    x16
+       tcr2    .req    x15
        mov_q   mair, MAIR_EL1_SET
        mov_q   tcr, TCR_T0SZ(IDMAP_VA_BITS) | TCR_T1SZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | \
                     TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
                     TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
+       mov     tcr2, xzr
 
        tcr_clear_errata_bits tcr, x9, x5
 
@@ -525,11 +527,16 @@ alternative_else_nop_endif
 #undef PTE_MAYBE_NG
 #undef PTE_MAYBE_SHARED
 
-       mov     x0, TCR2_EL1x_PIE
-       msr     REG_TCR2_EL1, x0
+       orr     tcr2, tcr2, TCR2_EL1x_PIE
 
 .Lskip_indirection:
 
+       mrs_s   x1, SYS_ID_AA64MMFR3_EL1
+       ubfx    x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4
+       cbz     x1, 1f
+       msr     REG_TCR2_EL1, tcr2
+1:
+
        /*
         * Prepare SCTLR
         */
@@ -538,4 +545,5 @@ alternative_else_nop_endif
 
        .unreq  mair
        .unreq  tcr
+       .unreq  tcr2
 SYM_FUNC_END(__cpu_setup)