memset(state, 0, sizeof(*state));
INIT_LIST_HEAD(&state->stack_vars);
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
state->regs[0].caller_saved = true;
state->regs[1].caller_saved = true;
state->regs[2].caller_saved = true;
needs_pointer = false;
else if (reg == dloc->fbreg || is_fbreg)
needs_pointer = false;
- else if (arch__is(dloc->arch, "x86") && reg == X86_REG_SP)
+ else if (arch__is_x86(dloc->arch) && reg == X86_REG_SP)
needs_pointer = false;
/* Get the type of the variable */
/* should match to is_stack_canary() in util/annotate.c */
static void setup_stack_canary(struct data_loc_info *dloc)
{
- if (arch__is(dloc->arch, "x86")) {
+ if (arch__is_x86(dloc->arch)) {
dloc->op->segment = INSN_SEG_X86_GS;
dloc->op->imm = true;
dloc->op->offset = 40;
/* Direct this-cpu access like "%gs:0x34740" */
if (dloc->op->segment == INSN_SEG_X86_GS && dloc->op->imm &&
- arch__is(dloc->arch, "x86")) {
+ arch__is_x86(dloc->arch)) {
pr_debug_dtp("this-cpu var");
addr = dloc->op->offset;
static int arch_supports_insn_tracking(struct data_loc_info *dloc)
{
- if ((arch__is(dloc->arch, "x86")) || (arch__is(dloc->arch, "powerpc")))
+ if ((arch__is_x86(dloc->arch)) || (arch__is_powerpc(dloc->arch)))
return 1;
return 0;
}
* %gs:0x18(%rbx). In that case it should skip the part.
*/
if (*str == arch->objdump.register_char) {
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
/* FIXME: Handle other segment registers */
if (!strncmp(str, "%gs:", 4))
op_loc->segment = INSN_SEG_X86_GS;
op_loc->reg2 = -1;
if (insn_str == NULL) {
- if (!arch__is(arch, "powerpc"))
+ if (!arch__is_powerpc(arch))
continue;
}
* required fields for op_loc, ie reg1, reg2, offset from the
* raw instruction.
*/
- if (arch__is(arch, "powerpc")) {
+ if (arch__is_powerpc(arch)) {
op_loc->mem_ref = mem_ref;
op_loc->multi_regs = multi_regs;
get_powerpc_regs(dl->raw.raw_insn, !i, op_loc);
} else {
char *s, *p = NULL;
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
/* FIXME: Handle other segment registers */
if (!strncmp(insn_str, "%gs:", 4)) {
op_loc->segment = INSN_SEG_X86_GS;
static bool is_stack_operation(const struct arch *arch, struct disasm_line *dl)
{
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
if (!strncmp(dl->ins.name, "push", 4) ||
!strncmp(dl->ins.name, "pop", 3) ||
!strncmp(dl->ins.name, "call", 4) ||
static bool is_stack_canary(const struct arch *arch, struct annotated_op_loc *loc)
{
/* On x86_64, %gs:40 is used for stack canary */
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
if (loc->segment == INSN_SEG_X86_GS && loc->imm &&
loc->offset == 40)
return true;
*/
static bool is_address_gen_insn(const struct arch *arch, struct disasm_line *dl)
{
- if (arch__is(arch, "x86")) {
+ if (arch__is_x86(arch)) {
if (!strncmp(dl->ins.name, "lea", 3))
return true;
}
}
/* This CPU access in kernel - pretend PC-relative addressing */
- if (dso__kernel(map__dso(ms->map)) && arch__is(arch, "x86") &&
+ if (dso__kernel(map__dso(ms->map)) && arch__is_x86(arch) &&
op_loc->segment == INSN_SEG_X86_GS && op_loc->imm) {
dloc.var_addr = op_loc->offset;
op_loc->reg1 = DWARF_REG_PC;
struct symbol *sym;
/* TODO: support more architectures */
- if (!arch__is(args->arch, "x86"))
+ if (!arch__is_x86(args->arch))
return;
if (insn->detail == NULL)
return bsearch(name, architectures, nmemb, sizeof(struct arch), arch__key_cmp);
}
-bool arch__is(const struct arch *arch, const char *name)
+bool arch__is_x86(const struct arch *arch)
{
- return !strcmp(arch->name, name);
+ return arch->e_machine == EM_386 || arch->e_machine == EM_X86_64;
+}
+
+bool arch__is_powerpc(const struct arch *arch)
+{
+ return arch->e_machine == EM_PPC || arch->e_machine == EM_PPC64;
}
static void ins_ops__delete(struct ins_operands *ops)
struct ins *ins;
const int nmemb = arch->nr_instructions;
- if (arch__is(arch, "powerpc")) {
+ if (arch__is_powerpc(arch)) {
/*
* For powerpc, identify the instruction ops
* from the opcode using raw_insn.
goto out_delete;
if (args->offset != -1) {
- if (arch__is(args->arch, "powerpc")) {
+ if (arch__is_powerpc(args->arch)) {
if (disasm_line__parse_powerpc(dl, args) < 0)
goto out_free_line;
} else if (disasm_line__parse(dl->al.line, &dl->ins.name, &dl->ops.raw) < 0)
* and typeoff, disassemble to mnemonic notation is not required in
* case of powerpc.
*/
- if (arch__is(args->arch, "powerpc")) {
+ if (arch__is_powerpc(args->arch)) {
extern const char *sort_order;
if (sort_order && !strstr(sort_order, "sym")) {
};
const struct arch *arch__find(const char *name);
-bool arch__is(const struct arch *arch, const char *name);
+bool arch__is_x86(const struct arch *arch);
+bool arch__is_powerpc(const struct arch *arch);
const struct ins_ops *ins__find(const struct arch *arch, const char *name, struct disasm_line *dl);
return errno;
init_llvm();
- if (arch__is(args->arch, "x86")) {
+ if (arch__is_x86(args->arch)) {
const char *triplet = is_64bit ? "x86_64-pc-linux" : "i686-pc-linux";
disasm = LLVMCreateDisasm(triplet, &storage, /*tag_type=*/0,