mips: limit cvt.s.l instruction translation to fp_mode64

The documentation says:
"For CVT.S.L, the result of this instruction is UNPREDICTABLE if the
processor is executing in the FR=0 32-bit FPU register model; it is
predictable if executing on a 64-bit FPU in the FR=1 mode, but not with
FR=0, and not on a 32-bit FPU."

Hence the fix.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3354

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 0a63875cbefe08cda03870cf17c5e680d018be9b..c10693c49f37ac57a8a32da046e8c1d9a831d5fb 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -13090,12 +13090,16 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
 
                   case 0x15:  /* L */
                      DIP("cvt.s.l %u, %u", fd, fs);
-                     calculateFCSR(fs, 0, CVTSL, False, 1);
-                     t0 = newTemp(Ity_I64);
-                     assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
+                     if (fp_mode64) {
+                        calculateFCSR(fs, 0, CVTSL, False, 1);
+                        t0 = newTemp(Ity_I64);
+                        assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
 
-                     putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
-                                 get_IR_roundingmode(), mkexpr(t0))));
+                        putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
+                                    get_IR_roundingmode(), mkexpr(t0))));
+                     } else {
+                        ILLEGAL_INSTRUCTON;
+                     }
                      break;
 
                   default: