+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
+ * testsuite/gas/aarch64/morello_insn.d: Likewise.
+ * testsuite/gas/aarch64/morello_insn.s: Likewise.
+ * testsuite/gas/aarch64/morello_ldst-c64.d: New file.
+ * testsuite/gas/aarch64/morello_ldst.d: Likewise.
+ * testsuite/gas/aarch64/morello_ldst.s: Likewise.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Identify Can.
.*: c2c25280 ret c20
.*: c2c25283 retr c20
.*: c2c25282 rets c20
+.*: c2c213e1 chksld csp
+.*: c2c233e1 chktgd csp
.*: c2c1d26b mov c11, c19
.*: c2c1d26b mov c11, c19
+.*: c2d38561 chkss c11, c19
.*: c2c1d3eb mov c11, csp
.*: c2c1d3eb mov c11, csp
+.*: c2df8561 chkss c11, csp
.*: c2c1d17f mov csp, c11
.*: c2c1d17f mov csp, c11
+.*: c2cb87e1 chkss csp, c11
.*: c2c1d3ff mov csp, csp
.*: c2c1d3ff mov csp, csp
+.*: c2df87e1 chkss csp, csp
.*: aa1f03e0 mov x0, xzr
+.*: c2c59020 cvtd c0, x1
+.*: c2c5d020 cvtdz c0, x1
+.*: c2c5b020 cvtp c0, x1
+.*: c2c5f020 cvtpz c0, x1
+.*: c2c71022 rrlen x2, x1
+.*: c2c73022 rrmask x2, x1
+.*: c2c151e7 cfhi x7, c15
+.*: c2c511e7 cvtd x7, c15
+.*: c2c531e7 cvtp x7, c15
+.*: c2c153e6 cfhi x6, csp
+.*: c2c513e6 cvtd x6, csp
+.*: c2c533e6 cvtp x6, csp
+.*: c2c011e7 gcbase x7, c15
+.*: c2c131e7 gcflgs x7, c15
+.*: c2c031e7 gclen x7, c15
+.*: c2c111e7 gclim x7, c15
+.*: c2c071e7 gcoff x7, c15
+.*: c2c0d1e7 gcperm x7, c15
+.*: c2c0b1e7 gcseal x7, c15
+.*: c2c091e7 gctag x7, c15
+.*: c2c0f1e7 gctype x7, c15
+.*: c2c051e7 gcvalue x7, c15
+.*: c2c013e6 gcbase x6, csp
+.*: c2c133e6 gcflgs x6, csp
+.*: c2c033e6 gclen x6, csp
+.*: c2c113e6 gclim x6, csp
+.*: c2c073e6 gcoff x6, csp
+.*: c2c0d3e6 gcperm x6, csp
+.*: c2c0b3e6 gcseal x6, csp
+.*: c2c093e6 gctag x6, csp
+.*: c2c0f3e6 gctype x6, csp
+.*: c2c053e6 gcvalue x6, csp
+.*: c2d4a7e1 chkeq csp, c20
+.*: c2d4a661 chkeq c19, c20
.*: 023fc135 add c21, c9, #0xff0
.*: 023ffd35 add c21, c9, #0xfff
.*: 0247f935 add c21, c9, #0x1fe, lsl #12
.*: c2e000c7 bicflgs c7, c6, #0
.*: c2ffe0c7 bicflgs c7, c6, #255
.*: c2e200c7 bicflgs c7, c6, #16
+.*: c2fff0c7 eorflgs c7, c6, #255
+.*: c2e010c7 eorflgs c7, c6, #0
+.*: c2fff0c7 eorflgs c7, c6, #255
+.*: c2e210c7 eorflgs c7, c6, #16
+.*: c2ffe8c7 orrflgs c7, c6, #255
+.*: c2e008c7 orrflgs c7, c6, #0
+.*: c2ffe8c7 orrflgs c7, c6, #255
+.*: c2e208c7 orrflgs c7, c6, #16
.*: c2ffe0df bicflgs csp, c6, #255
.*: c2e000df bicflgs csp, c6, #0
.*: c2ffe0df bicflgs csp, c6, #255
.*: c2e200df bicflgs csp, c6, #16
+.*: c2fff0df eorflgs csp, c6, #255
+.*: c2e010df eorflgs csp, c6, #0
+.*: c2fff0df eorflgs csp, c6, #255
+.*: c2e210df eorflgs csp, c6, #16
+.*: c2ffe8df orrflgs csp, c6, #255
+.*: c2e008df orrflgs csp, c6, #0
+.*: c2ffe8df orrflgs csp, c6, #255
+.*: c2e208df orrflgs csp, c6, #16
.*: c2ffe3e8 bicflgs c8, csp, #255
.*: c2e003e8 bicflgs c8, csp, #0
.*: c2ffe3e8 bicflgs c8, csp, #255
.*: c2e203e8 bicflgs c8, csp, #16
+.*: c2fff3e8 eorflgs c8, csp, #255
+.*: c2e013e8 eorflgs c8, csp, #0
+.*: c2fff3e8 eorflgs c8, csp, #255
+.*: c2e213e8 eorflgs c8, csp, #16
+.*: c2ffebe8 orrflgs c8, csp, #255
+.*: c2e00be8 orrflgs c8, csp, #0
+.*: c2ffebe8 orrflgs c8, csp, #255
+.*: c2e20be8 orrflgs c8, csp, #16
.*: c2ffe3ff bicflgs csp, csp, #255
.*: c2e003ff bicflgs csp, csp, #0
.*: c2ffe3ff bicflgs csp, csp, #255
.*: c2e203ff bicflgs csp, csp, #16
+.*: c2fff3ff eorflgs csp, csp, #255
+.*: c2e013ff eorflgs csp, csp, #0
+.*: c2fff3ff eorflgs csp, csp, #255
+.*: c2e213ff eorflgs csp, csp, #16
+.*: c2ffebff orrflgs csp, csp, #255
+.*: c2e00bff orrflgs csp, csp, #0
+.*: c2ffebff orrflgs csp, csp, #255
+.*: c2e20bff orrflgs csp, csp, #16
+.*: c2df9a11 alignd c17, c16, #63
+.*: c2cf1a11 alignd c17, c16, #30
+.*: c2c01a11 alignd c17, c16, #0
+.*: c2d01a11 alignd c17, c16, #32
+.*: c2dfda11 alignu c17, c16, #63
+.*: c2cf5a11 alignu c17, c16, #30
+.*: c2c05a11 alignu c17, c16, #0
+.*: c2d05a11 alignu c17, c16, #32
+.*: c2df9a1f alignd csp, c16, #63
+.*: c2cf1a1f alignd csp, c16, #30
+.*: c2c01a1f alignd csp, c16, #0
+.*: c2d01a1f alignd csp, c16, #32
+.*: c2dfda1f alignu csp, c16, #63
+.*: c2cf5a1f alignu csp, c16, #30
+.*: c2c05a1f alignu csp, c16, #0
+.*: c2d05a1f alignu csp, c16, #32
+.*: c2df9bf2 alignd c18, csp, #63
+.*: c2cf1bf2 alignd c18, csp, #30
+.*: c2c01bf2 alignd c18, csp, #0
+.*: c2d01bf2 alignd c18, csp, #32
+.*: c2dfdbf2 alignu c18, csp, #63
+.*: c2cf5bf2 alignu c18, csp, #30
+.*: c2c05bf2 alignu c18, csp, #0
+.*: c2d05bf2 alignu c18, csp, #32
+.*: c2df9bff alignd csp, csp, #63
+.*: c2cf1bff alignd csp, csp, #30
+.*: c2c01bff alignd csp, csp, #0
+.*: c2d01bff alignd csp, csp, #32
+.*: c2dfdbff alignu csp, csp, #63
+.*: c2cf5bff alignu csp, csp, #30
+.*: c2c05bff alignu csp, csp, #0
+.*: c2d05bff alignu csp, csp, #32
.*: c2d928c7 bicflgs c7, c6, x25
+.*: c2d9a8c7 eorflgs c7, c6, x25
+.*: c2d968c7 orrflgs c7, c6, x25
.*: c2d92be7 bicflgs c7, csp, x25
+.*: c2d9abe7 eorflgs c7, csp, x25
+.*: c2d96be7 orrflgs c7, csp, x25
.*: c2d928df bicflgs csp, c6, x25
+.*: c2d9a8df eorflgs csp, c6, x25
+.*: c2d968df orrflgs csp, c6, x25
.*: c2d92bff bicflgs csp, csp, x25
+.*: c2d9abff eorflgs csp, csp, x25
+.*: c2d96bff orrflgs csp, csp, x25
+.*: c2ee99a4 subs x4, c13, c14
.*: c2c4a440 blrs c29, c2, c4
.*: c2c48440 brs c29, c2, c4
.*: c2c4c440 rets c29, c2, c4
+.*: c2cd2482 cpytype c2, c4, c13
+.*: c2cd6482 cpyvalue c2, c4, c13
+.*: c2d9eac0 cthi c0, c22, x25
+.*: c2d9e89f cthi csp, c4, x25
+.*: c2f91816 cvt c22, c0, x25
+.*: c2f95816 cvtz c22, c0, x25
+.*: c2f91be4 cvt c4, csp, x25
+.*: c2f95be4 cvtz c4, csp, x25
+.*: c2d9c016 cvt x22, c0, c25
+.*: c2d9c3e4 cvt x4, csp, c25
+.*: c2d688ed chkssu c13, c7, c22
+.*: c2d68bed chkssu c13, csp, c22
+.*: c2df88ed chkssu c13, c7, csp
+.*: c2df8bed chkssu c13, csp, csp
+.*: c2cd0482 build c2, c4, c13
+.*: c2cd4482 cseal c2, c4, c13
+.*: c2cd049f build csp, c4, c13
+.*: c2cd449f cseal csp, c4, c13
+.*: c2cd07e2 build c2, csp, c13
+.*: c2cd47e2 cseal c2, csp, c13
+.*: c2cd07ff build csp, csp, c13
+.*: c2cd47ff cseal csp, csp, c13
+.*: c2df0482 build c2, c4, csp
+.*: c2df4482 cseal c2, c4, csp
+.*: c2df049f build csp, c4, csp
+.*: c2df449f cseal csp, c4, csp
+.*: c2df07e2 build c2, csp, csp
+.*: c2df47e2 cseal c2, csp, csp
+.*: c2df07ff build csp, csp, csp
+.*: c2df47ff cseal csp, csp, csp
.*: c2a4e131 add c17, c9, x4, sxtx
.*: c2a4f131 add c17, c9, x4, sxtx #4
.*: c2a4d131 add c17, c9, w4, sxtw #4
.*: c2a4d3ff add csp, csp, w4, sxtw #4
.*: c2a463ff add csp, csp, x4, uxtx
.*: c2a473ff add csp, csp, x4, uxtx #4
+.*: c2c30ced csel c13, c7, c3, eq // eq = none
+.*: c2c31ced csel c13, c7, c3, ne // ne = any
+.*: c2c32ced csel c13, c7, c3, cs // cs = hs, nlast
+.*: c2c32ced csel c13, c7, c3, cs // cs = hs, nlast
+.*: c2c33ced csel c13, c7, c3, cc // cc = lo, ul, last
+.*: c2c33ced csel c13, c7, c3, cc // cc = lo, ul, last
+.*: c2c34ced csel c13, c7, c3, mi // mi = first
+.*: c2c35ced csel c13, c7, c3, pl // pl = nfrst
+.*: c2c36ced csel c13, c7, c3, vs
+.*: c2c37ced csel c13, c7, c3, vc
+.*: c2c38ced csel c13, c7, c3, hi // hi = pmore
+.*: c2c39ced csel c13, c7, c3, ls // ls = plast
+.*: c2c3aced csel c13, c7, c3, ge // ge = tcont
+.*: c2c3bced csel c13, c7, c3, lt // lt = tstop
+.*: c2c3cced csel c13, c7, c3, gt
+.*: c2c3dced csel c13, c7, c3, le
+.*: c2c3eced csel c13, c7, c3, al
+.*: c2c3fced csel c13, c7, c3, nv
.*: c2c25280 ret c20
.*: c2c25283 retr c20
.*: c2c25282 rets c20
+.*: c2c213e1 chksld csp
+.*: c2c233e1 chktgd csp
.*: c2c1d26b mov c11, c19
.*: c2c1d26b mov c11, c19
+.*: c2d38561 chkss c11, c19
.*: c2c1d3eb mov c11, csp
.*: c2c1d3eb mov c11, csp
+.*: c2df8561 chkss c11, csp
.*: c2c1d17f mov csp, c11
.*: c2c1d17f mov csp, c11
+.*: c2cb87e1 chkss csp, c11
.*: c2c1d3ff mov csp, csp
.*: c2c1d3ff mov csp, csp
+.*: c2df87e1 chkss csp, csp
.*: aa1f03e0 mov x0, xzr
+.*: c2c59020 cvtd c0, x1
+.*: c2c5d020 cvtdz c0, x1
+.*: c2c5b020 cvtp c0, x1
+.*: c2c5f020 cvtpz c0, x1
+.*: c2c71022 rrlen x2, x1
+.*: c2c73022 rrmask x2, x1
+.*: c2c151e7 cfhi x7, c15
+.*: c2c511e7 cvtd x7, c15
+.*: c2c531e7 cvtp x7, c15
+.*: c2c153e6 cfhi x6, csp
+.*: c2c513e6 cvtd x6, csp
+.*: c2c533e6 cvtp x6, csp
+.*: c2c011e7 gcbase x7, c15
+.*: c2c131e7 gcflgs x7, c15
+.*: c2c031e7 gclen x7, c15
+.*: c2c111e7 gclim x7, c15
+.*: c2c071e7 gcoff x7, c15
+.*: c2c0d1e7 gcperm x7, c15
+.*: c2c0b1e7 gcseal x7, c15
+.*: c2c091e7 gctag x7, c15
+.*: c2c0f1e7 gctype x7, c15
+.*: c2c051e7 gcvalue x7, c15
+.*: c2c013e6 gcbase x6, csp
+.*: c2c133e6 gcflgs x6, csp
+.*: c2c033e6 gclen x6, csp
+.*: c2c113e6 gclim x6, csp
+.*: c2c073e6 gcoff x6, csp
+.*: c2c0d3e6 gcperm x6, csp
+.*: c2c0b3e6 gcseal x6, csp
+.*: c2c093e6 gctag x6, csp
+.*: c2c0f3e6 gctype x6, csp
+.*: c2c053e6 gcvalue x6, csp
+.*: c2d4a7e1 chkeq csp, c20
+.*: c2d4a661 chkeq c19, c20
.*: 023fc135 add c21, c9, #0xff0
.*: 023ffd35 add c21, c9, #0xfff
.*: 0247f935 add c21, c9, #0x1fe, lsl #12
.*: c2e000c7 bicflgs c7, c6, #0
.*: c2ffe0c7 bicflgs c7, c6, #255
.*: c2e200c7 bicflgs c7, c6, #16
+.*: c2fff0c7 eorflgs c7, c6, #255
+.*: c2e010c7 eorflgs c7, c6, #0
+.*: c2fff0c7 eorflgs c7, c6, #255
+.*: c2e210c7 eorflgs c7, c6, #16
+.*: c2ffe8c7 orrflgs c7, c6, #255
+.*: c2e008c7 orrflgs c7, c6, #0
+.*: c2ffe8c7 orrflgs c7, c6, #255
+.*: c2e208c7 orrflgs c7, c6, #16
.*: c2ffe0df bicflgs csp, c6, #255
.*: c2e000df bicflgs csp, c6, #0
.*: c2ffe0df bicflgs csp, c6, #255
.*: c2e200df bicflgs csp, c6, #16
+.*: c2fff0df eorflgs csp, c6, #255
+.*: c2e010df eorflgs csp, c6, #0
+.*: c2fff0df eorflgs csp, c6, #255
+.*: c2e210df eorflgs csp, c6, #16
+.*: c2ffe8df orrflgs csp, c6, #255
+.*: c2e008df orrflgs csp, c6, #0
+.*: c2ffe8df orrflgs csp, c6, #255
+.*: c2e208df orrflgs csp, c6, #16
.*: c2ffe3e8 bicflgs c8, csp, #255
.*: c2e003e8 bicflgs c8, csp, #0
.*: c2ffe3e8 bicflgs c8, csp, #255
.*: c2e203e8 bicflgs c8, csp, #16
+.*: c2fff3e8 eorflgs c8, csp, #255
+.*: c2e013e8 eorflgs c8, csp, #0
+.*: c2fff3e8 eorflgs c8, csp, #255
+.*: c2e213e8 eorflgs c8, csp, #16
+.*: c2ffebe8 orrflgs c8, csp, #255
+.*: c2e00be8 orrflgs c8, csp, #0
+.*: c2ffebe8 orrflgs c8, csp, #255
+.*: c2e20be8 orrflgs c8, csp, #16
.*: c2ffe3ff bicflgs csp, csp, #255
.*: c2e003ff bicflgs csp, csp, #0
.*: c2ffe3ff bicflgs csp, csp, #255
.*: c2e203ff bicflgs csp, csp, #16
+.*: c2fff3ff eorflgs csp, csp, #255
+.*: c2e013ff eorflgs csp, csp, #0
+.*: c2fff3ff eorflgs csp, csp, #255
+.*: c2e213ff eorflgs csp, csp, #16
+.*: c2ffebff orrflgs csp, csp, #255
+.*: c2e00bff orrflgs csp, csp, #0
+.*: c2ffebff orrflgs csp, csp, #255
+.*: c2e20bff orrflgs csp, csp, #16
+.*: c2df9a11 alignd c17, c16, #63
+.*: c2cf1a11 alignd c17, c16, #30
+.*: c2c01a11 alignd c17, c16, #0
+.*: c2d01a11 alignd c17, c16, #32
+.*: c2dfda11 alignu c17, c16, #63
+.*: c2cf5a11 alignu c17, c16, #30
+.*: c2c05a11 alignu c17, c16, #0
+.*: c2d05a11 alignu c17, c16, #32
+.*: c2df9a1f alignd csp, c16, #63
+.*: c2cf1a1f alignd csp, c16, #30
+.*: c2c01a1f alignd csp, c16, #0
+.*: c2d01a1f alignd csp, c16, #32
+.*: c2dfda1f alignu csp, c16, #63
+.*: c2cf5a1f alignu csp, c16, #30
+.*: c2c05a1f alignu csp, c16, #0
+.*: c2d05a1f alignu csp, c16, #32
+.*: c2df9bf2 alignd c18, csp, #63
+.*: c2cf1bf2 alignd c18, csp, #30
+.*: c2c01bf2 alignd c18, csp, #0
+.*: c2d01bf2 alignd c18, csp, #32
+.*: c2dfdbf2 alignu c18, csp, #63
+.*: c2cf5bf2 alignu c18, csp, #30
+.*: c2c05bf2 alignu c18, csp, #0
+.*: c2d05bf2 alignu c18, csp, #32
+.*: c2df9bff alignd csp, csp, #63
+.*: c2cf1bff alignd csp, csp, #30
+.*: c2c01bff alignd csp, csp, #0
+.*: c2d01bff alignd csp, csp, #32
+.*: c2dfdbff alignu csp, csp, #63
+.*: c2cf5bff alignu csp, csp, #30
+.*: c2c05bff alignu csp, csp, #0
+.*: c2d05bff alignu csp, csp, #32
.*: c2d928c7 bicflgs c7, c6, x25
+.*: c2d9a8c7 eorflgs c7, c6, x25
+.*: c2d968c7 orrflgs c7, c6, x25
.*: c2d92be7 bicflgs c7, csp, x25
+.*: c2d9abe7 eorflgs c7, csp, x25
+.*: c2d96be7 orrflgs c7, csp, x25
.*: c2d928df bicflgs csp, c6, x25
+.*: c2d9a8df eorflgs csp, c6, x25
+.*: c2d968df orrflgs csp, c6, x25
.*: c2d92bff bicflgs csp, csp, x25
+.*: c2d9abff eorflgs csp, csp, x25
+.*: c2d96bff orrflgs csp, csp, x25
+.*: c2ee99a4 subs x4, c13, c14
.*: c2c4a440 blrs c29, c2, c4
.*: c2c48440 brs c29, c2, c4
.*: c2c4c440 rets c29, c2, c4
+.*: c2cd2482 cpytype c2, c4, c13
+.*: c2cd6482 cpyvalue c2, c4, c13
+.*: c2d9eac0 cthi c0, c22, x25
+.*: c2d9e89f cthi csp, c4, x25
+.*: c2f91816 cvt c22, c0, x25
+.*: c2f95816 cvtz c22, c0, x25
+.*: c2f91be4 cvt c4, csp, x25
+.*: c2f95be4 cvtz c4, csp, x25
+.*: c2d9c016 cvt x22, c0, c25
+.*: c2d9c3e4 cvt x4, csp, c25
+.*: c2d688ed chkssu c13, c7, c22
+.*: c2d68bed chkssu c13, csp, c22
+.*: c2df88ed chkssu c13, c7, csp
+.*: c2df8bed chkssu c13, csp, csp
+.*: c2cd0482 build c2, c4, c13
+.*: c2cd4482 cseal c2, c4, c13
+.*: c2cd049f build csp, c4, c13
+.*: c2cd449f cseal csp, c4, c13
+.*: c2cd07e2 build c2, csp, c13
+.*: c2cd47e2 cseal c2, csp, c13
+.*: c2cd07ff build csp, csp, c13
+.*: c2cd47ff cseal csp, csp, c13
+.*: c2df0482 build c2, c4, csp
+.*: c2df4482 cseal c2, c4, csp
+.*: c2df049f build csp, c4, csp
+.*: c2df449f cseal csp, c4, csp
+.*: c2df07e2 build c2, csp, csp
+.*: c2df47e2 cseal c2, csp, csp
+.*: c2df07ff build csp, csp, csp
+.*: c2df47ff cseal csp, csp, csp
.*: c2a4e131 add c17, c9, x4, sxtx
.*: c2a4f131 add c17, c9, x4, sxtx #4
.*: c2a4d131 add c17, c9, w4, sxtw #4
.*: c2a4d3ff add csp, csp, w4, sxtw #4
.*: c2a463ff add csp, csp, x4, uxtx
.*: c2a473ff add csp, csp, x4, uxtx #4
+.*: c2c30ced csel c13, c7, c3, eq // eq = none
+.*: c2c31ced csel c13, c7, c3, ne // ne = any
+.*: c2c32ced csel c13, c7, c3, cs // cs = hs, nlast
+.*: c2c32ced csel c13, c7, c3, cs // cs = hs, nlast
+.*: c2c33ced csel c13, c7, c3, cc // cc = lo, ul, last
+.*: c2c33ced csel c13, c7, c3, cc // cc = lo, ul, last
+.*: c2c34ced csel c13, c7, c3, mi // mi = first
+.*: c2c35ced csel c13, c7, c3, pl // pl = nfrst
+.*: c2c36ced csel c13, c7, c3, vs
+.*: c2c37ced csel c13, c7, c3, vc
+.*: c2c38ced csel c13, c7, c3, hi // hi = pmore
+.*: c2c39ced csel c13, c7, c3, ls // ls = plast
+.*: c2c3aced csel c13, c7, c3, ge // ge = tcont
+.*: c2c3bced csel c13, c7, c3, lt // lt = tstop
+.*: c2c3cced csel c13, c7, c3, gt
+.*: c2c3dced csel c13, c7, c3, le
+.*: c2c3eced csel c13, c7, c3, al
+.*: c2c3fced csel c13, c7, c3, nv
.endm
morello_jump c20
+ .macro morello_csp cnsp
+ .irp op, chksld, chktgd
+ \op \cnsp
+ .endr
+ .endm
+morello_csp csp
+
// Two operands (dn).
.macro morello_cspcsp cdsp, cnsp
- .irp op, cpy, mov
+ .irp op, cpy, mov, chkss
\op \cdsp, \cnsp
.endr
.endm
mov c0, czr
+ .macro morello_cx cd, xn
+ .irp op, cvtd, cvtdz, cvtp, cvtpz
+ \op \cd, \xn
+ .endr
+ .endm
+morello_cx c0, x1
+
+ .macro morello_xx xd, xn
+ .irp op, rrlen, rrmask
+ \op \xd, \xn
+ .endr
+ .endm
+morello_xx x2, x1
+
+ .macro morello_xcsp xd, cnsp
+ .irp op, cfhi, cvtd, cvtp
+ \op \xd, \cnsp
+ .endr
+ .endm
+morello_xcsp x7, c15
+morello_xcsp x6, csp
+
+ .macro morello_gc_xc xd, cnsp
+ .irp op, gcbase, gcflgs, gclen, gclim, gcoff, gcperm, gcseal, gctag, gctype, gcvalue
+ \op \xd, \cnsp
+ .endr
+ .endm
+morello_gc_xc x7, c15
+morello_gc_xc x6, csp
+
+chkeq csp, c20
+chkeq c19, c20
+
// Three operands (dni)
.macro morello_addsub_imm cdsp, cnsp
morello_addsub_imm c21, csp
.macro morello_cspcspi8 cdsp, cnsp
- .irp op, bicflgs
+ .irp op, bicflgs, eorflgs, orrflgs
\op \cdsp, \cnsp, #0xff
\op \cdsp, \cnsp, #0
\op \cdsp, \cnsp, #0xff
morello_cspcspi8 c8, csp
morello_cspcspi8 csp, csp
+ .macro morello_cspcspi6 cdsp, cnsp
+ .irp op, alignd, alignu
+ \op \cdsp, \cnsp, #0x3f
+ \op \cdsp, \cnsp, #0x1e
+ \op \cdsp, \cnsp, #0
+ \op \cdsp, \cnsp, #0x20
+ .endr
+ .endm
+morello_cspcspi6 c17, c16
+morello_cspcspi6 csp, c16
+morello_cspcspi6 c18, csp
+morello_cspcspi6 csp, csp
+
// Three operands (dnm)
.macro morello_cspcspx cdsp, cnsp, xm
- .irp op, bicflgs
+ .irp op, bicflgs, eorflgs, orrflgs
\op \cdsp, \cnsp, \xm
.endr
.endm
morello_cspcspx csp, c6, x25
morello_cspcspx csp, csp, x25
+subs x4, c13, c14
+
.macro morello_jump_sealed cn, cm
.irp op, blrs, brs, rets
\op c29, \cn, \cm
.endm
morello_jump_sealed c2, c4
+ .macro morello_ccc cd, cn, cm
+ .irp op, cpytype, cpyvalue
+ \op \cd, \cn, \cm
+ .endr
+ .endm
+morello_ccc c2, c4, c13
+
+ .macro morello_cspcx cdsp, cn, xm
+ .irp op, cthi
+ \op \cdsp, \cn, \xm
+ .endr
+ .endm
+morello_cspcx c0, c22, x25
+morello_cspcx csp, c4, x25
+
+ .macro morello_ccspx cd, cnsp, xm
+ .irp op, cvt, cvtz
+ \op \cd, \cnsp, \xm
+ .endr
+ .endm
+morello_ccspx c22, c0, x25
+morello_ccspx c4, csp, x25
+
+ .macro morello_xcspc xd, cnsp, cm
+ .irp op, cvt
+ \op \xd, \cnsp, \cm
+ .endr
+ .endm
+morello_xcspc x22, c0, c25
+morello_xcspc x4, csp, c25
+
+ .macro morello_ccspcsp cd, cnsp, cmsp
+ .irp op, chkssu
+ \op \cd, \cnsp, \cmsp
+ .endr
+ .endm
+morello_ccspcsp c13, c7, c22
+morello_ccspcsp c13, csp, c22
+morello_ccspcsp c13, c7, csp
+morello_ccspcsp c13, csp, csp
+
+ .macro morello_cspcspcsp cdsp, cnsp, cmsp
+ .irp op, build, cseal
+ \op \cdsp, \cnsp, \cmsp
+ .endr
+ .endm
+morello_cspcspcsp c2, c4, c13
+morello_cspcspcsp csp, c4, c13
+morello_cspcspcsp c2, csp, c13
+morello_cspcspcsp csp, csp, c13
+morello_cspcspcsp c2, c4, csp
+morello_cspcspcsp csp, c4, csp
+morello_cspcspcsp c2, csp, csp
+morello_cspcspcsp csp, csp, csp
+
// Four operands (dnmi)
.macro morello_add_scalar cspd, cspn, rm
morello_add_scalar csp, c9, 4
morello_add_scalar c17, csp, 4
morello_add_scalar csp, csp, 4
+
+ .macro morello_csel cd, cn, cm
+ .irp cond, EQ, NE, CS, HS, CC, LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV
+ csel \cd, \cn, \cm, \cond
+ .endr
+ .endm
+morello_csel c13, c7, c3
--- /dev/null
+#as: -march=morello+c64 --defsym C64MODE=1
+#objdump: -dr
+#source: morello_ldst.s
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+.*: a2e47f02 casa c4, c2, \[c24\]
+.*: a2e4ff02 casal c4, c2, \[c24\]
+.*: a2a47f02 cas c4, c2, \[c24\]
+.*: a2a4ff02 casl c4, c2, \[c24\]
+.*: a2e47fe2 casa c4, c2, \[csp\]
+.*: a2e4ffe2 casal c4, c2, \[csp\]
+.*: a2a47fe2 cas c4, c2, \[csp\]
+.*: a2a4ffe2 casl c4, c2, \[csp\]
+.*: a2a48302 swpa c4, c2, \[c24\]
+.*: a2e48302 swpal c4, c2, \[c24\]
+.*: a2248302 swp c4, c2, \[c24\]
+.*: a2648302 swpl c4, c2, \[c24\]
+.*: a2a483e2 swpa c4, c2, \[csp\]
+.*: a2e483e2 swpal c4, c2, \[csp\]
+.*: a22483e2 swp c4, c2, \[csp\]
+.*: a26483e2 swpl c4, c2, \[csp\]
--- /dev/null
+#as: -march=morello
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+.*: a2e47d62 casa c4, c2, \[x11\]
+.*: a2e4fd62 casal c4, c2, \[x11\]
+.*: a2a47d62 cas c4, c2, \[x11\]
+.*: a2a4fd62 casl c4, c2, \[x11\]
+.*: a2e47fe2 casa c4, c2, \[sp\]
+.*: a2e4ffe2 casal c4, c2, \[sp\]
+.*: a2a47fe2 cas c4, c2, \[sp\]
+.*: a2a4ffe2 casl c4, c2, \[sp\]
+.*: a2a48162 swpa c4, c2, \[x11\]
+.*: a2e48162 swpal c4, c2, \[x11\]
+.*: a2248162 swp c4, c2, \[x11\]
+.*: a2648162 swpl c4, c2, \[x11\]
+.*: a2a483e2 swpa c4, c2, \[sp\]
+.*: a2e483e2 swpal c4, c2, \[sp\]
+.*: a22483e2 swp c4, c2, \[sp\]
+.*: a26483e2 swpl c4, c2, \[sp\]
--- /dev/null
+ .ifdef C64MODE
+ SP_ .req csp
+ VAREG .req c24
+ ALTSP .req sp
+ ALTVAREG .req x12
+ .else
+ SP_ .req sp
+ VAREG .req x11
+ ALTSP .req csp
+ ALTVAREG .req c21
+ .endif
+
+// Base Register
+ .macro morello_cas cs, ct, xnsp
+ .irp op, casa casal, cas, casl
+ \op \cs, \ct, [\xnsp]
+ .endr
+ .endm
+morello_cas c4, c2, VAREG
+morello_cas c4, c2, SP_
+
+ .macro morello_swp cs, ct, xnsp
+ .irp op, swpa, swpal, swp, swpl
+ \op \cs, \ct, [\xnsp]
+ .endr
+ .endm
+morello_swp c4, c2, VAREG
+morello_swp c4, c2, SP_
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * aarch64-tbl.h (QL2_A64C_X_CA, QL2_A64C_CA_X, QL2_A64C_X_X,
+ QL3_A64C_X_CA_CA, QL3_A64C_CA_CA_ADDR, QL4_A64C_CSEL): New
+ macros.
+ (aarch64_opcode_table): New instructions.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c (aarch64_ext_a64c_immv): New function.
QLF2(CA, CA), \
}
+#define QL2_A64C_X_CA \
+{ \
+ QLF2(X, CA), \
+}
+
+#define QL2_A64C_CA_X \
+{ \
+ QLF2(CA, X), \
+}
+
+#define QL2_A64C_X_X \
+{ \
+ QLF2(X, X), \
+}
+
#define QL3_A64C_CA_CA_NIL \
{ \
QLF3(CA, CA, NIL), \
QLF3(CA, CA, X), \
}
+#define QL3_A64C_X_CA_CA \
+{ \
+ QLF3(X, CA, CA), \
+}
+
#define QL3_A64C_CA_CA_CA \
{ \
QLF3(CA, CA, CA), \
}
+
+#define QL3_A64C_CA_CA_ADDR \
+{ \
+ QLF3(CA, CA, S_Q), \
+}
+/* e.g. CSEL <Cad>, <Can>, <Cam>, <cond>. */
+#define QL4_A64C_CSEL \
+{ \
+ QLF4(CA, CA, CA, NIL), \
+}
\f
/* Opcode table. */
A64C_INSN ("cpy", 0xc2c1d000, 0xfffffc00, a64c, 0, OP2 (Cad_SP, Can_SP), QL2_A64C_CA_CA, F_HAS_ALIAS),
A64C_INSN ("mov", 0xc2c1d000, 0xfffffc00, a64c, 0, OP2 (Cad_SP, Can_SP), QL2_A64C_CA_CA, F_ALIAS | F_P1),
A64C_INSN ("mov", 0x2a1f03e0, 0x7fffffe0, a64c, OP_MOV_C_ZR, OP2 (Cad, Can), QL2_A64C_CA_CA, F_ALIAS | F_SF | F_P1),
+ A64C_INSN ("cpytype", 0xc2c02400, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("cpyvalue", 0xc2c06400, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
A64C_INSN ("add", 0x02000000, 0xff800000, a64c, OP_A64C_ADD, OP3 (Cad_SP, Can_SP, AIMM), QL3_A64C_CA_CA_NIL, 0),
A64C_INSN ("add", 0xc2a00000, 0xffe00000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_Rm_EXT), QL3_A64C_CA_CA_R, 0),
A64C_INSN ("sub", 0x02800000, 0xff800000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_AIMM), QL3_A64C_CA_CA_NIL, 0),
+ A64C_INSN ("subs", 0xc2e09800, 0xffe0fc00, a64c, 0, OP3 (Rd, Can, Cam), QL3_A64C_X_CA_CA, F_HAS_ALIAS),
+ CORE_INSN ("cmp", 0xc2e0981f, 0xffe0fc1f, a64c, 0, OP2 (Can, Cam), QL2_A64C_CA_CA, F_ALIAS),
+ A64C_INSN ("alignd", 0xc2c01800, 0xffe07c00, a64c, 0, OP3 (Cad_SP, Can_SP, IMM_2), QL3_A64C_CA_CA_NIL, 0),
+ A64C_INSN ("alignu", 0xc2c05800, 0xffe07c00, a64c, 0, OP3 (Cad_SP, Can_SP, IMM_2), QL3_A64C_CA_CA_NIL, 0),
A64C_INSN ("bicflgs", 0xc2e00000, 0xffe01c00, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_IMM8), QL3_A64C_CA_CA_NIL, 0),
A64C_INSN ("bicflgs", 0xc2c02800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
A64C_INSN ("blr", 0xc2c23000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
A64C_INSN ("brr", 0xc2c21003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
A64C_INSN ("brs", 0xc2c21002, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
A64C_INSN ("brs", 0xc2c08400, 0xffe0fc1f, br_sealed, 0, OP3 (A64C_CST_REG, Can, Cam), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("build", 0xc2c00400, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Cam_SP), QL3_A64C_CA_CA_CA, 0),
A64C_INSN ("bx", 0xc2c273e0, 0xffffffff, a64c, 0, OP1 (A64C_IMMV4), {}, 0),
+
+ /* Compare and swap capabilities. */
+ A64C_INSN ("cas", 0xa2a07c00, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("casa", 0xa2e07c00, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("casal", 0xa2e0fc00, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("casl", 0xa2a0fc00, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+
+ A64C_INSN ("cfhi", 0xc2c15000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("chkeq", 0xc2c0a401, 0xffe0fc1f, a64c, 0, OP2 (Can_SP, Cam), QL2_A64C_CA_CA, 0),
+ A64C_INSN ("chkss", 0xc2c08401, 0xffe0fc1f, a64c, 0, OP2 (Can_SP, Cam_SP), QL2_A64C_CA_CA, 0),
+ A64C_INSN ("chksld", 0xc2c21001, 0xfffffc1f, a64c, 0, OP1 (Can_SP), QL1_A64C_CA, 0),
+ A64C_INSN ("chktgd", 0xc2c23001, 0xfffffc1f, a64c, 0, OP1 (Can_SP), QL1_A64C_CA, 0),
+ A64C_INSN ("chkssu", 0xc2c08800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can_SP, Cam_SP), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("cseal", 0xc2c04400, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Cam_SP), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("csel", 0xc2c00c00, 0xffe00c00, a64c, 0, OP4 (Cad, Can, Cam, COND), QL4_A64C_CSEL, 0),
+ A64C_INSN ("cthi", 0xc2c0e800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("cvt", 0xc2e01800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("cvt", 0xc2c0c000, 0xffe0fc00, a64c, 0, OP3 (Rd, Can_SP, Cam), QL3_A64C_X_CA_CA, 0),
+ A64C_INSN ("cvtd", 0xc2c59000, 0xfffffc00, a64c, 0, OP2 (Cad, Rn), QL2_A64C_CA_X, 0),
+ A64C_INSN ("cvtd", 0xc2c51000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("cvtdz", 0xc2c5d000, 0xfffffc00, a64c, 0, OP2 (Cad, Rn), QL2_A64C_CA_X, 0),
+ A64C_INSN ("cvtp", 0xc2c5b000, 0xfffffc00, a64c, 0, OP2 (Cad, Rn), QL2_A64C_CA_X, 0),
+ A64C_INSN ("cvtp", 0xc2c53000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("cvtpz", 0xc2c5f000, 0xfffffc00, a64c, 0, OP2 (Cad, Rn), QL2_A64C_CA_X, 0),
+ A64C_INSN ("cvtz", 0xc2e05800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("eorflgs", 0xc2c0a800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("eorflgs", 0xc2e01000, 0xffe01c00, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_IMM8), QL3_A64C_CA_CA_NIL, 0),
+ A64C_INSN ("orrflgs", 0xc2c06800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("orrflgs", 0xc2e00800, 0xffe01c00, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_IMM8), QL3_A64C_CA_CA_NIL, 0),
+ A64C_INSN ("gcbase", 0xc2c01000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gcflgs", 0xc2c13000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gclen", 0xc2c03000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gclim", 0xc2c11000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gcoff", 0xc2c07000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gcperm", 0xc2c0d000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gcseal", 0xc2c0b000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gctag", 0xc2c09000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gctype", 0xc2c0f000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+ A64C_INSN ("gcvalue", 0xc2c05000, 0xfffffc00, a64c, 0, OP2 (Rd, Can_SP), QL2_A64C_X_CA, 0),
+
+ /* Swap capabilities in memory. */
+ A64C_INSN ("swp", 0xa2208000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("swpa", 0xa2a08000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("swpal", 0xa2e08000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+ A64C_INSN ("swpl", 0xa2608000, 0xffe0fc00, a64c, 0, OP3 (Cas, Cat, ADDR_SIMPLE), QL3_A64C_CA_CA_ADDR, 0),
+
A64C_INSN ("ret", 0xc2c25000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, F_OPD0_OPT | F_DEFAULT (30)),
A64C_INSN ("retr", 0xc2c25003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
A64C_INSN ("rets", 0xc2c25002, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
A64C_INSN ("rets", 0xc2c0c400, 0xffe0fc1f, br_sealed, 0, OP3 (A64C_CST_REG, Can, Cam), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("rrlen", 0xc2c71000, 0xfffffc00, a64c, 0, OP2 (Rd, Rn), QL2_A64C_X_X, 0),
+ A64C_INSN ("rrmask", 0xc2c73000, 0xfffffc00, a64c, 0, OP2 (Rd, Rn), QL2_A64C_X_X, 0),
/* TME Instructions. */
_TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
projects / thirdparty / binutils-gdb.git / commitdiff
