Fix assert on ppc32 due to typo for GPR28

The below commit introduced a regression on ppc32
ommit 00d4667295a821fef9eb198abcb0c942dffb6045
Author: Ivo Raisr <ivosh@ivosh.net>
Date:   Wed Sep 6 08:10:36 2017 +0200

    Reorder allocatable registers for AMD64, X86, and PPC so that the callee saved are listed first.

    Helper calls always trash all caller saved registers. By listing the callee saved
    first then VEX register allocator (both v2 and v3) is more likely to pick them
    and does not need to spill that much before helper calls.

Investigation/fix done by Ivo.

diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
index 8ee789a51b021646fd3e2cea0aa776b439a6af8d..27b3b38df2efe5fb357ca687ee4a572e42f32e7e 100644 (file)
--- a/VEX/priv/host_ppc_defs.h
+++ b/VEX/priv/host_ppc_defs.h
@@ -71,7 +71,7 @@ ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24,  10, 10); }
 ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25,  11, 11); }
 ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26,  12, 12); }
 ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27,  13, 13); }
-ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28,  14, 44); }
+ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28,  14, 14); }
 
 ST_IN HReg hregPPC_GPR3  ( Bool mode64 ) { return GPR(mode64,  3,  15, 15); }
 ST_IN HReg hregPPC_GPR4  ( Bool mode64 ) { return GPR(mode64,  4,  16, 16); }