}
};
+static bool shstk_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK);
+}
+
+static const VMStateDescription vmstate_shstk = {
+ .name = "cpu/cet_shstk",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = shstk_needed,
+ .fields = (VMStateField[]) {
+ /* pl0_ssp has been covered by vmstate_pl0_ssp. */
+ VMSTATE_UINT64(env.pl1_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl2_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl3_ssp, X86CPU),
+#ifdef TARGET_X86_64
+ VMSTATE_UINT64(env.int_ssp_table, X86CPU),
+#endif
+ VMSTATE_UINT64(env.guest_ssp, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool cet_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) ||
+ (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT));
+}
+
+static const VMStateDescription vmstate_cet = {
+ .name = "cpu/cet",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = cet_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.u_cet, X86CPU),
+ VMSTATE_UINT64(env.s_cet, X86CPU),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * const []) {
+ &vmstate_shstk,
+ NULL,
+ },
+};
+
const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
&vmstate_arch_lbr,
&vmstate_triple_fault,
&vmstate_pl0_ssp,
+ &vmstate_cet,
NULL
}
};