Fix some register-field decoding bugs for SSE. Nasty. There has to

be a more foolproof way of doing this.

git-svn-id: svn://svn.valgrind.org/vex/trunk@976

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index 469031a7d9178f62f5b2a9c0d03a69e33927b924..e5125efa70035462ee703167f26859b8f18edfbe 100644 (file)
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -7055,9 +7055,9 @@ static ULong dis_SSE_E_to_G_lo32 ( Prefix pfx, ULong delta,
    Int     alen;
    IRTemp  addr;
    UChar   rm = getUChar(delta);
-   IRExpr* gpart = getXMMReg(gregOfRM(rm));
+   IRExpr* gpart = getXMMReg(gregOfRexRM(pfx,rm));
    if (epartIsReg(rm)) {
-      putXMMReg( gregOfRM(rm), 
+      putXMMReg( gregOfRexRM(pfx,rm), 
                  binop(op, gpart,
                            getXMMReg(eregOfRexRM(pfx,rm))) );
       DIP("%s %s,%s\n", opname,
@@ -7359,7 +7359,7 @@ static ULong dis_SSEcmp_E_to_G ( Prefix pfx, ULong delta,
    }
 
    if (needNot && all_lanes) {
-      putXMMReg( gregOfRM(rm), 
+      putXMMReg( gregOfRexRM(pfx,rm), 
                  unop(Iop_NotV128, mkexpr(plain)) );
    }
    else