net/mlx5: Modify LSB bitmask in temperature event to include only the first bit

[ Upstream commit 633f16d7e07c129a36b882c05379e01ce5bdb542 ]

In the sensor_count field of the MTEWE register, bits 1-62 are
supported only for unmanaged switches, not for NICs, and bit 63
is reserved for internal use.

To prevent confusing output that may include set bits that are
not relevant to NIC sensors, we update the bitmask to retain only
the first bit, which corresponds to the sensor ASIC.

Signed-off-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/events.c b/drivers/net/ethernet/mellanox/mlx5/core/events.c
index a1ac3a654962e445448bbba95cce1e67e81857c6..080aee3e3f9bba798ff3e573eb609f16f89f54a5 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/events.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/events.c
@@ -160,6 +160,10 @@ static int temp_warn(struct notifier_block *nb, unsigned long type, void *data)
        u64 value_msb;
 
        value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb);
+       /* bit 1-63 are not supported for NICs,
+        * hence read only bit 0 (asic) from lsb.
+        */
+       value_lsb &= 0x1;
        value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb);
 
        mlx5_core_warn(events->dev,