include $(top_srcdir)/Makefile.tool-tests.am
-EXTRA_DIST =
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = \
+ insn_test_move_X0.stdout.exp insn_test_move_X0.stderr.exp \
+ insn_test_move_X0.vgtest \
+ insn_test_move_X1.stdout.exp insn_test_move_X1.stderr.exp \
+ insn_test_move_X1.vgtest \
+ insn_test_move_Y0.stdout.exp insn_test_move_Y0.stderr.exp \
+ insn_test_move_Y0.vgtest \
+ insn_test_move_Y1.stdout.exp insn_test_move_Y1.stderr.exp \
+ insn_test_move_Y1.vgtest \
+ insn_test_movei_X0.stdout.exp insn_test_movei_X0.stderr.exp \
+ insn_test_movei_X0.vgtest \
+ insn_test_movei_X1.stdout.exp insn_test_movei_X1.stderr.exp \
+ insn_test_movei_X1.vgtest \
+ insn_test_movei_Y0.stdout.exp insn_test_movei_Y0.stderr.exp \
+ insn_test_movei_Y0.vgtest \
+ insn_test_movei_Y1.stdout.exp insn_test_movei_Y1.stderr.exp \
+ insn_test_movei_Y1.vgtest \
+ insn_test_moveli_X0.stdout.exp insn_test_moveli_X0.stderr.exp \
+ insn_test_moveli_X0.vgtest \
+ insn_test_moveli_X1.stdout.exp insn_test_moveli_X1.stderr.exp \
+ insn_test_moveli_X1.vgtest \
+ insn_test_prefetch_X1.stdout.exp insn_test_prefetch_X1.stderr.exp \
+ insn_test_prefetch_X1.vgtest \
+ insn_test_prefetch_Y2.stdout.exp insn_test_prefetch_Y2.stderr.exp \
+ insn_test_prefetch_Y2.vgtest \
+ insn_test_prefetch_l1_X1.stdout.exp \
+ insn_test_prefetch_l1_X1.stderr.exp \
+ insn_test_prefetch_l1_X1.vgtest \
+ insn_test_prefetch_l1_Y2.stdout.exp \
+ insn_test_prefetch_l1_Y2.stderr.exp \
+ insn_test_prefetch_l1_Y2.vgtest \
+ insn_test_prefetch_l2_X1.stdout.exp \
+ insn_test_prefetch_l2_X1.stderr.exp \
+ insn_test_prefetch_l2_X1.vgtest \
+ insn_test_prefetch_l2_Y2.stdout.exp \
+ insn_test_prefetch_l2_Y2.stderr.exp \
+ insn_test_prefetch_l2_Y2.vgtest \
+ insn_test_prefetch_l3_X1.stdout.exp \
+ insn_test_prefetch_l3_X1.stderr.exp \
+ insn_test_prefetch_l3_X1.vgtest \
+ insn_test_prefetch_l3_Y2.stdout.exp \
+ insn_test_prefetch_l3_Y2.stderr.exp \
+ insn_test_prefetch_l3_Y2.vgtest \
+ insn_test_add_X0.stdout.exp insn_test_add_X0.stderr.exp \
+ insn_test_add_X0.vgtest \
+ insn_test_add_X1.stdout.exp insn_test_add_X1.stderr.exp \
+ insn_test_add_X1.vgtest \
+ insn_test_add_Y0.stdout.exp insn_test_add_Y0.stderr.exp \
+ insn_test_add_Y0.vgtest \
+ insn_test_add_Y1.stdout.exp insn_test_add_Y1.stderr.exp \
+ insn_test_add_Y1.vgtest \
+ insn_test_addi_X0.stdout.exp insn_test_addi_X0.stderr.exp \
+ insn_test_addi_X0.vgtest \
+ insn_test_addi_X1.stdout.exp insn_test_addi_X1.stderr.exp \
+ insn_test_addi_X1.vgtest \
+ insn_test_addi_Y0.stdout.exp insn_test_addi_Y0.stderr.exp \
+ insn_test_addi_Y0.vgtest \
+ insn_test_addi_Y1.stdout.exp insn_test_addi_Y1.stderr.exp \
+ insn_test_addi_Y1.vgtest \
+ insn_test_addli_X0.stdout.exp insn_test_addli_X0.stderr.exp \
+ insn_test_addli_X0.vgtest \
+ insn_test_addli_X1.stdout.exp insn_test_addli_X1.stderr.exp \
+ insn_test_addli_X1.vgtest \
+ insn_test_addx_X0.stdout.exp insn_test_addx_X0.stderr.exp \
+ insn_test_addx_X0.vgtest \
+ insn_test_addx_X1.stdout.exp insn_test_addx_X1.stderr.exp \
+ insn_test_addx_X1.vgtest \
+ insn_test_addx_Y0.stdout.exp insn_test_addx_Y0.stderr.exp \
+ insn_test_addx_Y0.vgtest \
+ insn_test_addx_Y1.stdout.exp insn_test_addx_Y1.stderr.exp \
+ insn_test_addx_Y1.vgtest \
+ insn_test_addxi_X0.stdout.exp insn_test_addxi_X0.stderr.exp \
+ insn_test_addxi_X0.vgtest \
+ insn_test_addxi_X1.stdout.exp insn_test_addxi_X1.stderr.exp \
+ insn_test_addxi_X1.vgtest \
+ insn_test_addxi_Y0.stdout.exp insn_test_addxi_Y0.stderr.exp \
+ insn_test_addxi_Y0.vgtest \
+ insn_test_addxi_Y1.stdout.exp insn_test_addxi_Y1.stderr.exp \
+ insn_test_addxi_Y1.vgtest \
+ insn_test_addxli_X0.stdout.exp insn_test_addxli_X0.stderr.exp \
+ insn_test_addxli_X0.vgtest \
+ insn_test_addxli_X1.stdout.exp insn_test_addxli_X1.stderr.exp \
+ insn_test_addxli_X1.vgtest \
+ insn_test_addxsc_X0.stdout.exp insn_test_addxsc_X0.stderr.exp \
+ insn_test_addxsc_X0.vgtest \
+ insn_test_addxsc_X1.stdout.exp insn_test_addxsc_X1.stderr.exp \
+ insn_test_addxsc_X1.vgtest \
+ insn_test_and_X0.stdout.exp insn_test_and_X0.stderr.exp \
+ insn_test_and_X0.vgtest \
+ insn_test_and_X1.stdout.exp insn_test_and_X1.stderr.exp \
+ insn_test_and_X1.vgtest \
+ insn_test_and_Y0.stdout.exp insn_test_and_Y0.stderr.exp \
+ insn_test_and_Y0.vgtest \
+ insn_test_and_Y1.stdout.exp insn_test_and_Y1.stderr.exp \
+ insn_test_and_Y1.vgtest \
+ insn_test_andi_X0.stdout.exp insn_test_andi_X0.stderr.exp \
+ insn_test_andi_X0.vgtest \
+ insn_test_andi_X1.stdout.exp insn_test_andi_X1.stderr.exp \
+ insn_test_andi_X1.vgtest \
+ insn_test_andi_Y0.stdout.exp insn_test_andi_Y0.stderr.exp \
+ insn_test_andi_Y0.vgtest \
+ insn_test_andi_Y1.stdout.exp insn_test_andi_Y1.stderr.exp \
+ insn_test_andi_Y1.vgtest \
+ insn_test_beqz_X1.stdout.exp insn_test_beqz_X1.stderr.exp \
+ insn_test_beqz_X1.vgtest \
+ insn_test_beqzt_X1.stdout.exp insn_test_beqzt_X1.stderr.exp \
+ insn_test_beqzt_X1.vgtest \
+ insn_test_bfexts_X0.stdout.exp insn_test_bfexts_X0.stderr.exp \
+ insn_test_bfexts_X0.vgtest \
+ insn_test_bfextu_X0.stdout.exp insn_test_bfextu_X0.stderr.exp \
+ insn_test_bfextu_X0.vgtest \
+ insn_test_bfins_X0.stdout.exp insn_test_bfins_X0.stderr.exp \
+ insn_test_bfins_X0.vgtest \
+ insn_test_bgez_X1.stdout.exp insn_test_bgez_X1.stderr.exp \
+ insn_test_bgez_X1.vgtest \
+ insn_test_bgezt_X1.stdout.exp insn_test_bgezt_X1.stderr.exp \
+ insn_test_bgezt_X1.vgtest \
+ insn_test_bgtz_X1.stdout.exp insn_test_bgtz_X1.stderr.exp \
+ insn_test_bgtz_X1.vgtest \
+ insn_test_bgtzt_X1.stdout.exp insn_test_bgtzt_X1.stderr.exp \
+ insn_test_bgtzt_X1.vgtest \
+ insn_test_blbc_X1.stdout.exp insn_test_blbc_X1.stderr.exp \
+ insn_test_blbc_X1.vgtest \
+ insn_test_blbct_X1.stdout.exp insn_test_blbct_X1.stderr.exp \
+ insn_test_blbct_X1.vgtest \
+ insn_test_blbs_X1.stdout.exp insn_test_blbs_X1.stderr.exp \
+ insn_test_blbs_X1.vgtest \
+ insn_test_blbst_X1.stdout.exp insn_test_blbst_X1.stderr.exp \
+ insn_test_blbst_X1.vgtest \
+ insn_test_blez_X1.stdout.exp insn_test_blez_X1.stderr.exp \
+ insn_test_blez_X1.vgtest \
+ insn_test_blezt_X1.stdout.exp insn_test_blezt_X1.stderr.exp \
+ insn_test_blezt_X1.vgtest \
+ insn_test_bltz_X1.stdout.exp insn_test_bltz_X1.stderr.exp \
+ insn_test_bltz_X1.vgtest \
+ insn_test_bltzt_X1.stdout.exp insn_test_bltzt_X1.stderr.exp \
+ insn_test_bltzt_X1.vgtest \
+ insn_test_bnez_X1.stdout.exp insn_test_bnez_X1.stderr.exp \
+ insn_test_bnez_X1.vgtest \
+ insn_test_bnezt_X1.stdout.exp insn_test_bnezt_X1.stderr.exp \
+ insn_test_bnezt_X1.vgtest \
+ insn_test_clz_X0.stdout.exp insn_test_clz_X0.stderr.exp \
+ insn_test_clz_X0.vgtest \
+ insn_test_clz_Y0.stdout.exp insn_test_clz_Y0.stderr.exp \
+ insn_test_clz_Y0.vgtest \
+ insn_test_cmoveqz_X0.stdout.exp insn_test_cmoveqz_X0.stderr.exp \
+ insn_test_cmoveqz_X0.vgtest \
+ insn_test_cmoveqz_Y0.stdout.exp insn_test_cmoveqz_Y0.stderr.exp \
+ insn_test_cmoveqz_Y0.vgtest \
+ insn_test_cmovnez_X0.stdout.exp insn_test_cmovnez_X0.stderr.exp \
+ insn_test_cmovnez_X0.vgtest \
+ insn_test_cmovnez_Y0.stdout.exp insn_test_cmovnez_Y0.stderr.exp \
+ insn_test_cmovnez_Y0.vgtest \
+ insn_test_cmpeq_X0.stdout.exp insn_test_cmpeq_X0.stderr.exp \
+ insn_test_cmpeq_X0.vgtest \
+ insn_test_cmpeq_X1.stdout.exp insn_test_cmpeq_X1.stderr.exp \
+ insn_test_cmpeq_X1.vgtest \
+ insn_test_cmpeq_Y0.stdout.exp insn_test_cmpeq_Y0.stderr.exp \
+ insn_test_cmpeq_Y0.vgtest \
+ insn_test_cmpeq_Y1.stdout.exp insn_test_cmpeq_Y1.stderr.exp \
+ insn_test_cmpeq_Y1.vgtest \
+ insn_test_cmpeqi_X0.stdout.exp insn_test_cmpeqi_X0.stderr.exp \
+ insn_test_cmpeqi_X0.vgtest \
+ insn_test_cmpeqi_X1.stdout.exp insn_test_cmpeqi_X1.stderr.exp \
+ insn_test_cmpeqi_X1.vgtest \
+ insn_test_cmpeqi_Y0.stdout.exp insn_test_cmpeqi_Y0.stderr.exp \
+ insn_test_cmpeqi_Y0.vgtest \
+ insn_test_cmpeqi_Y1.stdout.exp insn_test_cmpeqi_Y1.stderr.exp \
+ insn_test_cmpeqi_Y1.vgtest \
+ insn_test_cmples_X0.stdout.exp insn_test_cmples_X0.stderr.exp \
+ insn_test_cmples_X0.vgtest \
+ insn_test_cmples_X1.stdout.exp insn_test_cmples_X1.stderr.exp \
+ insn_test_cmples_X1.vgtest \
+ insn_test_cmples_Y0.stdout.exp insn_test_cmples_Y0.stderr.exp \
+ insn_test_cmples_Y0.vgtest \
+ insn_test_cmples_Y1.stdout.exp insn_test_cmples_Y1.stderr.exp \
+ insn_test_cmples_Y1.vgtest \
+ insn_test_cmpleu_X0.stdout.exp insn_test_cmpleu_X0.stderr.exp \
+ insn_test_cmpleu_X0.vgtest \
+ insn_test_cmpleu_X1.stdout.exp insn_test_cmpleu_X1.stderr.exp \
+ insn_test_cmpleu_X1.vgtest \
+ insn_test_cmpleu_Y0.stdout.exp insn_test_cmpleu_Y0.stderr.exp \
+ insn_test_cmpleu_Y0.vgtest \
+ insn_test_cmpleu_Y1.stdout.exp insn_test_cmpleu_Y1.stderr.exp \
+ insn_test_cmpleu_Y1.vgtest \
+ insn_test_cmplts_X0.stdout.exp insn_test_cmplts_X0.stderr.exp \
+ insn_test_cmplts_X0.vgtest \
+ insn_test_cmplts_X1.stdout.exp insn_test_cmplts_X1.stderr.exp \
+ insn_test_cmplts_X1.vgtest \
+ insn_test_cmplts_Y0.stdout.exp insn_test_cmplts_Y0.stderr.exp \
+ insn_test_cmplts_Y0.vgtest \
+ insn_test_cmplts_Y1.stdout.exp insn_test_cmplts_Y1.stderr.exp \
+ insn_test_cmplts_Y1.vgtest \
+ insn_test_cmpltsi_X0.stdout.exp insn_test_cmpltsi_X0.stderr.exp \
+ insn_test_cmpltsi_X0.vgtest \
+ insn_test_cmpltsi_X1.stdout.exp insn_test_cmpltsi_X1.stderr.exp \
+ insn_test_cmpltsi_X1.vgtest \
+ insn_test_cmpltsi_Y0.stdout.exp insn_test_cmpltsi_Y0.stderr.exp \
+ insn_test_cmpltsi_Y0.vgtest \
+ insn_test_cmpltsi_Y1.stdout.exp insn_test_cmpltsi_Y1.stderr.exp \
+ insn_test_cmpltsi_Y1.vgtest \
+ insn_test_cmpltu_X0.stdout.exp insn_test_cmpltu_X0.stderr.exp \
+ insn_test_cmpltu_X0.vgtest \
+ insn_test_cmpltu_X1.stdout.exp insn_test_cmpltu_X1.stderr.exp \
+ insn_test_cmpltu_X1.vgtest \
+ insn_test_cmpltu_Y0.stdout.exp insn_test_cmpltu_Y0.stderr.exp \
+ insn_test_cmpltu_Y0.vgtest \
+ insn_test_cmpltu_Y1.stdout.exp insn_test_cmpltu_Y1.stderr.exp \
+ insn_test_cmpltu_Y1.vgtest \
+ insn_test_cmpltui_X0.stdout.exp insn_test_cmpltui_X0.stderr.exp \
+ insn_test_cmpltui_X0.vgtest \
+ insn_test_cmpltui_X1.stdout.exp insn_test_cmpltui_X1.stderr.exp \
+ insn_test_cmpltui_X1.vgtest \
+ insn_test_cmpne_X0.stdout.exp insn_test_cmpne_X0.stderr.exp \
+ insn_test_cmpne_X0.vgtest \
+ insn_test_cmpne_X1.stdout.exp insn_test_cmpne_X1.stderr.exp \
+ insn_test_cmpne_X1.vgtest \
+ insn_test_cmpne_Y0.stdout.exp insn_test_cmpne_Y0.stderr.exp \
+ insn_test_cmpne_Y0.vgtest \
+ insn_test_cmpne_Y1.stdout.exp insn_test_cmpne_Y1.stderr.exp \
+ insn_test_cmpne_Y1.vgtest \
+ insn_test_cmul_X0.stdout.exp insn_test_cmul_X0.stderr.exp \
+ insn_test_cmul_X0.vgtest \
+ insn_test_cmula_X0.stdout.exp insn_test_cmula_X0.stderr.exp \
+ insn_test_cmula_X0.vgtest \
+ insn_test_cmulaf_X0.stdout.exp insn_test_cmulaf_X0.stderr.exp \
+ insn_test_cmulaf_X0.vgtest \
+ insn_test_cmulf_X0.stdout.exp insn_test_cmulf_X0.stderr.exp \
+ insn_test_cmulf_X0.vgtest \
+ insn_test_cmulfr_X0.stdout.exp insn_test_cmulfr_X0.stderr.exp \
+ insn_test_cmulfr_X0.vgtest \
+ insn_test_cmulh_X0.stdout.exp insn_test_cmulh_X0.stderr.exp \
+ insn_test_cmulh_X0.vgtest \
+ insn_test_cmulhr_X0.stdout.exp insn_test_cmulhr_X0.stderr.exp \
+ insn_test_cmulhr_X0.vgtest \
+ insn_test_crc32_32_X0.stdout.exp insn_test_crc32_32_X0.stderr.exp \
+ insn_test_crc32_32_X0.vgtest \
+ insn_test_crc32_8_X0.stdout.exp insn_test_crc32_8_X0.stderr.exp \
+ insn_test_crc32_8_X0.vgtest \
+ insn_test_ctz_X0.stdout.exp insn_test_ctz_X0.stderr.exp \
+ insn_test_ctz_X0.vgtest \
+ insn_test_ctz_Y0.stdout.exp insn_test_ctz_Y0.stderr.exp \
+ insn_test_ctz_Y0.vgtest \
+ insn_test_dblalign_X0.stdout.exp insn_test_dblalign_X0.stderr.exp \
+ insn_test_dblalign_X0.vgtest \
+ insn_test_dblalign2_X0.stdout.exp insn_test_dblalign2_X0.stderr.exp \
+ insn_test_dblalign2_X0.vgtest \
+ insn_test_dblalign2_X1.stdout.exp insn_test_dblalign2_X1.stderr.exp \
+ insn_test_dblalign2_X1.vgtest \
+ insn_test_dblalign4_X0.stdout.exp insn_test_dblalign4_X0.stderr.exp \
+ insn_test_dblalign4_X0.vgtest \
+ insn_test_dblalign4_X1.stdout.exp insn_test_dblalign4_X1.stderr.exp \
+ insn_test_dblalign4_X1.vgtest \
+ insn_test_dblalign6_X0.stdout.exp insn_test_dblalign6_X0.stderr.exp \
+ insn_test_dblalign6_X0.vgtest \
+ insn_test_dblalign6_X1.stdout.exp insn_test_dblalign6_X1.stderr.exp \
+ insn_test_dblalign6_X1.vgtest \
+ insn_test_dtlbpr_X1.stdout.exp insn_test_dtlbpr_X1.stderr.exp \
+ insn_test_dtlbpr_X1.vgtest \
+ insn_test_fdouble_add_flags_X0.stdout.exp \
+ insn_test_fdouble_add_flags_X0.stderr.exp \
+ insn_test_fdouble_add_flags_X0.vgtest \
+ insn_test_fdouble_addsub_X0.stdout.exp \
+ insn_test_fdouble_addsub_X0.stderr.exp \
+ insn_test_fdouble_addsub_X0.vgtest \
+ insn_test_fdouble_mul_flags_X0.stdout.exp \
+ insn_test_fdouble_mul_flags_X0.stderr.exp \
+ insn_test_fdouble_mul_flags_X0.vgtest \
+ insn_test_fdouble_pack1_X0.stdout.exp \
+ insn_test_fdouble_pack1_X0.stderr.exp \
+ insn_test_fdouble_pack1_X0.vgtest \
+ insn_test_fdouble_pack2_X0.stdout.exp \
+ insn_test_fdouble_pack2_X0.stderr.exp \
+ insn_test_fdouble_pack2_X0.vgtest \
+ insn_test_fdouble_sub_flags_X0.stdout.exp \
+ insn_test_fdouble_sub_flags_X0.stderr.exp \
+ insn_test_fdouble_sub_flags_X0.vgtest \
+ insn_test_fdouble_unpack_max_X0.stdout.exp \
+ insn_test_fdouble_unpack_max_X0.stderr.exp \
+ insn_test_fdouble_unpack_max_X0.vgtest \
+ insn_test_fdouble_unpack_min_X0.stdout.exp \
+ insn_test_fdouble_unpack_min_X0.stderr.exp \
+ insn_test_fdouble_unpack_min_X0.vgtest \
+ insn_test_flushwb_X1.stdout.exp insn_test_flushwb_X1.stderr.exp \
+ insn_test_flushwb_X1.vgtest \
+ insn_test_fnop_X0.stdout.exp insn_test_fnop_X0.stderr.exp \
+ insn_test_fnop_X0.vgtest \
+ insn_test_fnop_X1.stdout.exp insn_test_fnop_X1.stderr.exp \
+ insn_test_fnop_X1.vgtest \
+ insn_test_fnop_Y0.stdout.exp insn_test_fnop_Y0.stderr.exp \
+ insn_test_fnop_Y0.vgtest \
+ insn_test_fnop_Y1.stdout.exp insn_test_fnop_Y1.stderr.exp \
+ insn_test_fnop_Y1.vgtest \
+ insn_test_fsingle_add1_X0.stdout.exp \
+ insn_test_fsingle_add1_X0.stderr.exp \
+ insn_test_fsingle_add1_X0.vgtest \
+ insn_test_fsingle_addsub2_X0.stdout.exp \
+ insn_test_fsingle_addsub2_X0.stderr.exp \
+ insn_test_fsingle_addsub2_X0.vgtest \
+ insn_test_fsingle_mul1_X0.stdout.exp \
+ insn_test_fsingle_mul1_X0.stderr.exp \
+ insn_test_fsingle_mul1_X0.vgtest \
+ insn_test_fsingle_mul2_X0.stdout.exp \
+ insn_test_fsingle_mul2_X0.stderr.exp \
+ insn_test_fsingle_mul2_X0.vgtest \
+ insn_test_fsingle_pack1_X0.stdout.exp \
+ insn_test_fsingle_pack1_X0.stderr.exp \
+ insn_test_fsingle_pack1_X0.vgtest \
+ insn_test_fsingle_pack1_Y0.stdout.exp \
+ insn_test_fsingle_pack1_Y0.stderr.exp \
+ insn_test_fsingle_pack1_Y0.vgtest \
+ insn_test_fsingle_pack2_X0.stdout.exp \
+ insn_test_fsingle_pack2_X0.stderr.exp \
+ insn_test_fsingle_pack2_X0.vgtest \
+ insn_test_fsingle_sub1_X0.stdout.exp \
+ insn_test_fsingle_sub1_X0.stderr.exp \
+ insn_test_fsingle_sub1_X0.vgtest \
+ insn_test_icoh_X1.stdout.exp insn_test_icoh_X1.stderr.exp \
+ insn_test_icoh_X1.vgtest \
+ insn_test_j_X1.stdout.exp insn_test_j_X1.stderr.exp \
+ insn_test_j_X1.vgtest \
+ insn_test_jal_X1.stdout.exp insn_test_jal_X1.stderr.exp \
+ insn_test_jal_X1.vgtest \
+ insn_test_jalr_X1.stdout.exp insn_test_jalr_X1.stderr.exp \
+ insn_test_jalr_X1.vgtest \
+ insn_test_jalr_Y1.stdout.exp insn_test_jalr_Y1.stderr.exp \
+ insn_test_jalr_Y1.vgtest \
+ insn_test_jalrp_X1.stdout.exp insn_test_jalrp_X1.stderr.exp \
+ insn_test_jalrp_X1.vgtest \
+ insn_test_jalrp_Y1.stdout.exp insn_test_jalrp_Y1.stderr.exp \
+ insn_test_jalrp_Y1.vgtest \
+ insn_test_jr_X1.stdout.exp insn_test_jr_X1.stderr.exp \
+ insn_test_jr_X1.vgtest \
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+ insn_test_v2mults_X0.vgtest \
+ insn_test_v2mz_X0.stdout.exp insn_test_v2mz_X0.stderr.exp \
+ insn_test_v2mz_X0.vgtest \
+ insn_test_v2mz_X1.stdout.exp insn_test_v2mz_X1.stderr.exp \
+ insn_test_v2mz_X1.vgtest \
+ insn_test_v2packh_X0.stdout.exp insn_test_v2packh_X0.stderr.exp \
+ insn_test_v2packh_X0.vgtest \
+ insn_test_v2packh_X1.stdout.exp insn_test_v2packh_X1.stderr.exp \
+ insn_test_v2packh_X1.vgtest \
+ insn_test_v2packl_X0.stdout.exp insn_test_v2packl_X0.stderr.exp \
+ insn_test_v2packl_X0.vgtest \
+ insn_test_v2packl_X1.stdout.exp insn_test_v2packl_X1.stderr.exp \
+ insn_test_v2packl_X1.vgtest \
+ insn_test_v2packuc_X0.stdout.exp insn_test_v2packuc_X0.stderr.exp \
+ insn_test_v2packuc_X0.vgtest \
+ insn_test_v2packuc_X1.stdout.exp insn_test_v2packuc_X1.stderr.exp \
+ insn_test_v2packuc_X1.vgtest \
+ insn_test_v2sadas_X0.stdout.exp insn_test_v2sadas_X0.stderr.exp \
+ insn_test_v2sadas_X0.vgtest \
+ insn_test_v2sadau_X0.stdout.exp insn_test_v2sadau_X0.stderr.exp \
+ insn_test_v2sadau_X0.vgtest \
+ insn_test_v2sads_X0.stdout.exp insn_test_v2sads_X0.stderr.exp \
+ insn_test_v2sads_X0.vgtest \
+ insn_test_v2sadu_X0.stdout.exp insn_test_v2sadu_X0.stderr.exp \
+ insn_test_v2sadu_X0.vgtest \
+ insn_test_v2shl_X0.stdout.exp insn_test_v2shl_X0.stderr.exp \
+ insn_test_v2shl_X0.vgtest \
+ insn_test_v2shl_X1.stdout.exp insn_test_v2shl_X1.stderr.exp \
+ insn_test_v2shl_X1.vgtest \
+ insn_test_v2shli_X0.stdout.exp insn_test_v2shli_X0.stderr.exp \
+ insn_test_v2shli_X0.vgtest \
+ insn_test_v2shli_X1.stdout.exp insn_test_v2shli_X1.stderr.exp \
+ insn_test_v2shli_X1.vgtest \
+ insn_test_v2shlsc_X0.stdout.exp insn_test_v2shlsc_X0.stderr.exp \
+ insn_test_v2shlsc_X0.vgtest \
+ insn_test_v2shlsc_X1.stdout.exp insn_test_v2shlsc_X1.stderr.exp \
+ insn_test_v2shlsc_X1.vgtest \
+ insn_test_v2shrs_X0.stdout.exp insn_test_v2shrs_X0.stderr.exp \
+ insn_test_v2shrs_X0.vgtest \
+ insn_test_v2shrs_X1.stdout.exp insn_test_v2shrs_X1.stderr.exp \
+ insn_test_v2shrs_X1.vgtest \
+ insn_test_v2shrsi_X0.stdout.exp insn_test_v2shrsi_X0.stderr.exp \
+ insn_test_v2shrsi_X0.vgtest \
+ insn_test_v2shrsi_X1.stdout.exp insn_test_v2shrsi_X1.stderr.exp \
+ insn_test_v2shrsi_X1.vgtest \
+ insn_test_v2shru_X0.stdout.exp insn_test_v2shru_X0.stderr.exp \
+ insn_test_v2shru_X0.vgtest \
+ insn_test_v2shru_X1.stdout.exp insn_test_v2shru_X1.stderr.exp \
+ insn_test_v2shru_X1.vgtest \
+ insn_test_v2shrui_X0.stdout.exp insn_test_v2shrui_X0.stderr.exp \
+ insn_test_v2shrui_X0.vgtest \
+ insn_test_v2shrui_X1.stdout.exp insn_test_v2shrui_X1.stderr.exp \
+ insn_test_v2shrui_X1.vgtest \
+ insn_test_v2sub_X0.stdout.exp insn_test_v2sub_X0.stderr.exp \
+ insn_test_v2sub_X0.vgtest \
+ insn_test_v2sub_X1.stdout.exp insn_test_v2sub_X1.stderr.exp \
+ insn_test_v2sub_X1.vgtest \
+ insn_test_v2subsc_X0.stdout.exp insn_test_v2subsc_X0.stderr.exp \
+ insn_test_v2subsc_X0.vgtest \
+ insn_test_v2subsc_X1.stdout.exp insn_test_v2subsc_X1.stderr.exp \
+ insn_test_v2subsc_X1.vgtest \
+ insn_test_v4add_X0.stdout.exp insn_test_v4add_X0.stderr.exp \
+ insn_test_v4add_X0.vgtest \
+ insn_test_v4add_X1.stdout.exp insn_test_v4add_X1.stderr.exp \
+ insn_test_v4add_X1.vgtest \
+ insn_test_v4addsc_X0.stdout.exp insn_test_v4addsc_X0.stderr.exp \
+ insn_test_v4addsc_X0.vgtest \
+ insn_test_v4addsc_X1.stdout.exp insn_test_v4addsc_X1.stderr.exp \
+ insn_test_v4addsc_X1.vgtest \
+ insn_test_v4int_h_X0.stdout.exp insn_test_v4int_h_X0.stderr.exp \
+ insn_test_v4int_h_X0.vgtest \
+ insn_test_v4int_h_X1.stdout.exp insn_test_v4int_h_X1.stderr.exp \
+ insn_test_v4int_h_X1.vgtest \
+ insn_test_v4int_l_X0.stdout.exp insn_test_v4int_l_X0.stderr.exp \
+ insn_test_v4int_l_X0.vgtest \
+ insn_test_v4int_l_X1.stdout.exp insn_test_v4int_l_X1.stderr.exp \
+ insn_test_v4int_l_X1.vgtest \
+ insn_test_v4packsc_X0.stdout.exp insn_test_v4packsc_X0.stderr.exp \
+ insn_test_v4packsc_X0.vgtest \
+ insn_test_v4packsc_X1.stdout.exp insn_test_v4packsc_X1.stderr.exp \
+ insn_test_v4packsc_X1.vgtest \
+ insn_test_v4shl_X0.stdout.exp insn_test_v4shl_X0.stderr.exp \
+ insn_test_v4shl_X0.vgtest \
+ insn_test_v4shl_X1.stdout.exp insn_test_v4shl_X1.stderr.exp \
+ insn_test_v4shl_X1.vgtest \
+ insn_test_v4shlsc_X0.stdout.exp insn_test_v4shlsc_X0.stderr.exp \
+ insn_test_v4shlsc_X0.vgtest \
+ insn_test_v4shlsc_X1.stdout.exp insn_test_v4shlsc_X1.stderr.exp \
+ insn_test_v4shlsc_X1.vgtest \
+ insn_test_v4shrs_X0.stdout.exp insn_test_v4shrs_X0.stderr.exp \
+ insn_test_v4shrs_X0.vgtest \
+ insn_test_v4shrs_X1.stdout.exp insn_test_v4shrs_X1.stderr.exp \
+ insn_test_v4shrs_X1.vgtest \
+ insn_test_v4shru_X0.stdout.exp insn_test_v4shru_X0.stderr.exp \
+ insn_test_v4shru_X0.vgtest \
+ insn_test_v4shru_X1.stdout.exp insn_test_v4shru_X1.stderr.exp \
+ insn_test_v4shru_X1.vgtest \
+ insn_test_v4sub_X0.stdout.exp insn_test_v4sub_X0.stderr.exp \
+ insn_test_v4sub_X0.vgtest \
+ insn_test_v4sub_X1.stdout.exp insn_test_v4sub_X1.stderr.exp \
+ insn_test_v4sub_X1.vgtest \
+ insn_test_v4subsc_X0.stdout.exp insn_test_v4subsc_X0.stderr.exp \
+ insn_test_v4subsc_X0.vgtest \
+ insn_test_v4subsc_X1.stdout.exp insn_test_v4subsc_X1.stderr.exp \
+ insn_test_v4subsc_X1.vgtest \
+ insn_test_wh64_X1.stdout.exp insn_test_wh64_X1.stderr.exp \
+ insn_test_wh64_X1.vgtest \
+ insn_test_xor_X0.stdout.exp insn_test_xor_X0.stderr.exp \
+ insn_test_xor_X0.vgtest \
+ insn_test_xor_X1.stdout.exp insn_test_xor_X1.stderr.exp \
+ insn_test_xor_X1.vgtest \
+ insn_test_xor_Y0.stdout.exp insn_test_xor_Y0.stderr.exp \
+ insn_test_xor_Y0.vgtest \
+ insn_test_xor_Y1.stdout.exp insn_test_xor_Y1.stderr.exp \
+ insn_test_xor_Y1.vgtest \
+ insn_test_xori_X0.stdout.exp insn_test_xori_X0.stderr.exp \
+ insn_test_xori_X0.vgtest \
+ insn_test_xori_X1.stdout.exp insn_test_xori_X1.stderr.exp \
+ insn_test_xori_X1.vgtest
+
+bin_PROGRAMS = gen_insn_test
+
+insn_tests = \
+ insn_test_move_X0 \
+ insn_test_move_X1 \
+ insn_test_move_Y0 \
+ insn_test_move_Y1 \
+ insn_test_movei_X0 \
+ insn_test_movei_X1 \
+ insn_test_movei_Y0 \
+ insn_test_movei_Y1 \
+ insn_test_moveli_X0 \
+ insn_test_moveli_X1 \
+ insn_test_prefetch_X1 \
+ insn_test_prefetch_Y2 \
+ insn_test_prefetch_l1_X1 \
+ insn_test_prefetch_l1_Y2 \
+ insn_test_prefetch_l2_X1 \
+ insn_test_prefetch_l2_Y2 \
+ insn_test_prefetch_l3_X1 \
+ insn_test_prefetch_l3_Y2 \
+ insn_test_add_X0 \
+ insn_test_add_X1 \
+ insn_test_add_Y0 \
+ insn_test_add_Y1 \
+ insn_test_addi_X0 \
+ insn_test_addi_X1 \
+ insn_test_addi_Y0 \
+ insn_test_addi_Y1 \
+ insn_test_addli_X0 \
+ insn_test_addli_X1 \
+ insn_test_addx_X0 \
+ insn_test_addx_X1 \
+ insn_test_addx_Y0 \
+ insn_test_addx_Y1 \
+ insn_test_addxi_X0 \
+ insn_test_addxi_X1 \
+ insn_test_addxi_Y0 \
+ insn_test_addxi_Y1 \
+ insn_test_addxli_X0 \
+ insn_test_addxli_X1 \
+ insn_test_addxsc_X0 \
+ insn_test_addxsc_X1 \
+ insn_test_and_X0 \
+ insn_test_and_X1 \
+ insn_test_and_Y0 \
+ insn_test_and_Y1 \
+ insn_test_andi_X0 \
+ insn_test_andi_X1 \
+ insn_test_andi_Y0 \
+ insn_test_andi_Y1 \
+ insn_test_beqz_X1 \
+ insn_test_beqzt_X1 \
+ insn_test_bfexts_X0 \
+ insn_test_bfextu_X0 \
+ insn_test_bfins_X0 \
+ insn_test_bgez_X1 \
+ insn_test_bgezt_X1 \
+ insn_test_bgtz_X1 \
+ insn_test_bgtzt_X1 \
+ insn_test_blbc_X1 \
+ insn_test_blbct_X1 \
+ insn_test_blbs_X1 \
+ insn_test_blbst_X1 \
+ insn_test_blez_X1 \
+ insn_test_blezt_X1 \
+ insn_test_bltz_X1 \
+ insn_test_bltzt_X1 \
+ insn_test_bnez_X1 \
+ insn_test_bnezt_X1 \
+ insn_test_clz_X0 \
+ insn_test_clz_Y0 \
+ insn_test_cmoveqz_X0 \
+ insn_test_cmoveqz_Y0 \
+ insn_test_cmovnez_X0 \
+ insn_test_cmovnez_Y0 \
+ insn_test_cmpeq_X0 \
+ insn_test_cmpeq_X1 \
+ insn_test_cmpeq_Y0 \
+ insn_test_cmpeq_Y1 \
+ insn_test_cmpeqi_X0 \
+ insn_test_cmpeqi_X1 \
+ insn_test_cmpeqi_Y0 \
+ insn_test_cmpeqi_Y1 \
+ insn_test_cmples_X0 \
+ insn_test_cmples_X1 \
+ insn_test_cmples_Y0 \
+ insn_test_cmples_Y1 \
+ insn_test_cmpleu_X0 \
+ insn_test_cmpleu_X1 \
+ insn_test_cmpleu_Y0 \
+ insn_test_cmpleu_Y1 \
+ insn_test_cmplts_X0 \
+ insn_test_cmplts_X1 \
+ insn_test_cmplts_Y0 \
+ insn_test_cmplts_Y1 \
+ insn_test_cmpltsi_X0 \
+ insn_test_cmpltsi_X1 \
+ insn_test_cmpltsi_Y0 \
+ insn_test_cmpltsi_Y1 \
+ insn_test_cmpltu_X0 \
+ insn_test_cmpltu_X1 \
+ insn_test_cmpltu_Y0 \
+ insn_test_cmpltu_Y1 \
+ insn_test_cmpltui_X0 \
+ insn_test_cmpltui_X1 \
+ insn_test_cmpne_X0 \
+ insn_test_cmpne_X1 \
+ insn_test_cmpne_Y0 \
+ insn_test_cmpne_Y1 \
+ insn_test_cmul_X0 \
+ insn_test_cmula_X0 \
+ insn_test_cmulaf_X0 \
+ insn_test_cmulf_X0 \
+ insn_test_cmulfr_X0 \
+ insn_test_cmulh_X0 \
+ insn_test_cmulhr_X0 \
+ insn_test_crc32_32_X0 \
+ insn_test_crc32_8_X0 \
+ insn_test_ctz_X0 \
+ insn_test_ctz_Y0 \
+ insn_test_dblalign_X0 \
+ insn_test_dblalign2_X0 \
+ insn_test_dblalign2_X1 \
+ insn_test_dblalign4_X0 \
+ insn_test_dblalign4_X1 \
+ insn_test_dblalign6_X0 \
+ insn_test_dblalign6_X1 \
+ insn_test_dtlbpr_X1 \
+ insn_test_fdouble_add_flags_X0 \
+ insn_test_fdouble_addsub_X0 \
+ insn_test_fdouble_mul_flags_X0 \
+ insn_test_fdouble_pack1_X0 \
+ insn_test_fdouble_pack2_X0 \
+ insn_test_fdouble_sub_flags_X0 \
+ insn_test_fdouble_unpack_max_X0 \
+ insn_test_fdouble_unpack_min_X0 \
+ insn_test_flushwb_X1 \
+ insn_test_fnop_X0 \
+ insn_test_fnop_X1 \
+ insn_test_fnop_Y0 \
+ insn_test_fnop_Y1 \
+ insn_test_fsingle_add1_X0 \
+ insn_test_fsingle_addsub2_X0 \
+ insn_test_fsingle_mul1_X0 \
+ insn_test_fsingle_mul2_X0 \
+ insn_test_fsingle_pack1_X0 \
+ insn_test_fsingle_pack1_Y0 \
+ insn_test_fsingle_pack2_X0 \
+ insn_test_fsingle_sub1_X0 \
+ insn_test_icoh_X1 \
+ insn_test_j_X1 \
+ insn_test_jal_X1 \
+ insn_test_jalr_X1 \
+ insn_test_jalr_Y1 \
+ insn_test_jalrp_X1 \
+ insn_test_jalrp_Y1 \
+ insn_test_jr_X1 \
+ insn_test_jr_Y1 \
+ insn_test_jrp_X1 \
+ insn_test_jrp_Y1 \
+ insn_test_ld_X1 \
+ insn_test_ld_Y2 \
+ insn_test_ld1s_X1 \
+ insn_test_ld1s_Y2 \
+ insn_test_ld1s_add_X1 \
+ insn_test_ld1u_X1 \
+ insn_test_ld1u_Y2 \
+ insn_test_ld1u_add_X1 \
+ insn_test_ld2s_X1 \
+ insn_test_ld2s_Y2 \
+ insn_test_ld2u_X1 \
+ insn_test_ld2u_Y2 \
+ insn_test_ld4s_X1 \
+ insn_test_ld4s_add_X1 \
+ insn_test_ld4u_X1 \
+ insn_test_ld4u_Y2 \
+ insn_test_ld4u_add_X1 \
+ insn_test_ld_add_X1 \
+ insn_test_ldna_X1 \
+ insn_test_ldna_add_X1 \
+ insn_test_ldnt_X1 \
+ insn_test_ldnt1s_X1 \
+ insn_test_ldnt1s_add_X1 \
+ insn_test_ldnt1u_X1 \
+ insn_test_ldnt1u_add_X1 \
+ insn_test_ldnt2s_X1 \
+ insn_test_ldnt2s_add_X1 \
+ insn_test_ldnt2u_add_X1 \
+ insn_test_ldnt4s_X1 \
+ insn_test_ldnt4s_add_X1 \
+ insn_test_ldnt4u_X1 \
+ insn_test_ldnt4u_add_X1 \
+ insn_test_ldnt_add_X1 \
+ insn_test_lnk_X1 \
+ insn_test_lnk_Y1 \
+ insn_test_mf_X1 \
+ insn_test_mm_X0 \
+ insn_test_mnz_X0 \
+ insn_test_mnz_X1 \
+ insn_test_mnz_Y0 \
+ insn_test_mnz_Y1 \
+ insn_test_mul_hs_hs_X0 \
+ insn_test_mul_hs_hs_Y0 \
+ insn_test_mul_hs_hu_X0 \
+ insn_test_mul_hs_ls_X0 \
+ insn_test_mul_hs_lu_X0 \
+ insn_test_mul_hu_hu_X0 \
+ insn_test_mul_hu_hu_Y0 \
+ insn_test_mul_hu_lu_X0 \
+ insn_test_mul_ls_ls_X0 \
+ insn_test_mul_ls_ls_Y0 \
+ insn_test_mul_ls_lu_X0 \
+ insn_test_mul_lu_lu_X0 \
+ insn_test_mul_lu_lu_Y0 \
+ insn_test_mula_hs_hs_X0 \
+ insn_test_mula_hs_hs_Y0 \
+ insn_test_mula_hs_hu_X0 \
+ insn_test_mula_hs_ls_X0 \
+ insn_test_mula_hs_lu_X0 \
+ insn_test_mula_hu_hu_X0 \
+ insn_test_mula_hu_hu_Y0 \
+ insn_test_mula_hu_ls_X0 \
+ insn_test_mula_hu_lu_X0 \
+ insn_test_mula_ls_ls_X0 \
+ insn_test_mula_ls_ls_Y0 \
+ insn_test_mula_ls_lu_X0 \
+ insn_test_mula_lu_lu_X0 \
+ insn_test_mula_lu_lu_Y0 \
+ insn_test_mulax_X0 \
+ insn_test_mulax_Y0 \
+ insn_test_mulx_X0 \
+ insn_test_mulx_Y0 \
+ insn_test_mz_X0 \
+ insn_test_mz_X1 \
+ insn_test_mz_Y0 \
+ insn_test_mz_Y1 \
+ insn_test_nop_X0 \
+ insn_test_nop_X1 \
+ insn_test_nop_Y0 \
+ insn_test_nop_Y1 \
+ insn_test_nor_X0 \
+ insn_test_nor_X1 \
+ insn_test_nor_Y0 \
+ insn_test_nor_Y1 \
+ insn_test_or_X0 \
+ insn_test_or_X1 \
+ insn_test_or_Y0 \
+ insn_test_or_Y1 \
+ insn_test_ori_X0 \
+ insn_test_ori_X1 \
+ insn_test_pcnt_X0 \
+ insn_test_pcnt_Y0 \
+ insn_test_revbits_X0 \
+ insn_test_revbits_Y0 \
+ insn_test_revbytes_X0 \
+ insn_test_revbytes_Y0 \
+ insn_test_rotl_X0 \
+ insn_test_rotl_X1 \
+ insn_test_rotl_Y0 \
+ insn_test_rotl_Y1 \
+ insn_test_rotli_X0 \
+ insn_test_rotli_X1 \
+ insn_test_rotli_Y0 \
+ insn_test_rotli_Y1 \
+ insn_test_shl_X0 \
+ insn_test_shl_X1 \
+ insn_test_shl_Y0 \
+ insn_test_shl_Y1 \
+ insn_test_shl16insli_X0 \
+ insn_test_shl16insli_X1 \
+ insn_test_shl1add_X0 \
+ insn_test_shl1add_X1 \
+ insn_test_shl1add_Y0 \
+ insn_test_shl1add_Y1 \
+ insn_test_shl1addx_X0 \
+ insn_test_shl1addx_X1 \
+ insn_test_shl1addx_Y0 \
+ insn_test_shl1addx_Y1 \
+ insn_test_shl2add_X0 \
+ insn_test_shl2add_X1 \
+ insn_test_shl2add_Y0 \
+ insn_test_shl2add_Y1 \
+ insn_test_shl2addx_X0 \
+ insn_test_shl2addx_X1 \
+ insn_test_shl2addx_Y0 \
+ insn_test_shl2addx_Y1 \
+ insn_test_shl3add_X0 \
+ insn_test_shl3add_X1 \
+ insn_test_shl3add_Y0 \
+ insn_test_shl3add_Y1 \
+ insn_test_shl3addx_X0 \
+ insn_test_shl3addx_X1 \
+ insn_test_shl3addx_Y0 \
+ insn_test_shl3addx_Y1 \
+ insn_test_shli_X0 \
+ insn_test_shli_X1 \
+ insn_test_shli_Y0 \
+ insn_test_shli_Y1 \
+ insn_test_shlx_X0 \
+ insn_test_shlx_X1 \
+ insn_test_shlxi_X0 \
+ insn_test_shlxi_X1 \
+ insn_test_shrs_X0 \
+ insn_test_shrs_X1 \
+ insn_test_shrs_Y0 \
+ insn_test_shrs_Y1 \
+ insn_test_shrsi_X0 \
+ insn_test_shrsi_X1 \
+ insn_test_shrsi_Y0 \
+ insn_test_shrsi_Y1 \
+ insn_test_shru_X0 \
+ insn_test_shru_X1 \
+ insn_test_shru_Y0 \
+ insn_test_shru_Y1 \
+ insn_test_shrui_X0 \
+ insn_test_shrui_X1 \
+ insn_test_shrui_Y0 \
+ insn_test_shrui_Y1 \
+ insn_test_shrux_X0 \
+ insn_test_shrux_X1 \
+ insn_test_shufflebytes_X0 \
+ insn_test_st_X1 \
+ insn_test_st_Y2 \
+ insn_test_st1_X1 \
+ insn_test_st1_Y2 \
+ insn_test_st1_add_X1 \
+ insn_test_st2_X1 \
+ insn_test_st2_Y2 \
+ insn_test_st2_add_X1 \
+ insn_test_st4_X1 \
+ insn_test_st4_Y2 \
+ insn_test_st4_add_X1 \
+ insn_test_st_add_X1 \
+ insn_test_stnt_X1 \
+ insn_test_stnt1_X1 \
+ insn_test_stnt2_X1 \
+ insn_test_stnt2_add_X1 \
+ insn_test_stnt4_X1 \
+ insn_test_stnt4_add_X1 \
+ insn_test_stnt_add_X1 \
+ insn_test_sub_X0 \
+ insn_test_sub_X1 \
+ insn_test_sub_Y0 \
+ insn_test_sub_Y1 \
+ insn_test_subx_X0 \
+ insn_test_subx_X1 \
+ insn_test_subx_Y0 \
+ insn_test_subx_Y1 \
+ insn_test_tblidxb0_X0 \
+ insn_test_tblidxb0_Y0 \
+ insn_test_tblidxb1_X0 \
+ insn_test_tblidxb1_Y0 \
+ insn_test_tblidxb2_X0 \
+ insn_test_tblidxb2_Y0 \
+ insn_test_tblidxb3_X0 \
+ insn_test_tblidxb3_Y0 \
+ insn_test_v1add_X0 \
+ insn_test_v1add_X1 \
+ insn_test_v1adduc_X0 \
+ insn_test_v1adduc_X1 \
+ insn_test_v1adiffu_X0 \
+ insn_test_v1avgu_X0 \
+ insn_test_v1cmpeq_X0 \
+ insn_test_v1cmpeq_X1 \
+ insn_test_v1cmpeqi_X0 \
+ insn_test_v1cmpeqi_X1 \
+ insn_test_v1cmples_X0 \
+ insn_test_v1cmples_X1 \
+ insn_test_v1cmpleu_X0 \
+ insn_test_v1cmpleu_X1 \
+ insn_test_v1cmplts_X0 \
+ insn_test_v1cmplts_X1 \
+ insn_test_v1cmpltu_X0 \
+ insn_test_v1cmpltu_X1 \
+ insn_test_v1cmpne_X0 \
+ insn_test_v1cmpne_X1 \
+ insn_test_v1ddotpu_X0 \
+ insn_test_v1ddotpua_X0 \
+ insn_test_v1ddotpus_X0 \
+ insn_test_v1ddotpusa_X0 \
+ insn_test_v1dotp_X0 \
+ insn_test_v1dotpa_X0 \
+ insn_test_v1dotpu_X0 \
+ insn_test_v1dotpua_X0 \
+ insn_test_v1dotpus_X0 \
+ insn_test_v1dotpusa_X0 \
+ insn_test_v1int_h_X0 \
+ insn_test_v1int_h_X1 \
+ insn_test_v1int_l_X0 \
+ insn_test_v1int_l_X1 \
+ insn_test_v1maxu_X0 \
+ insn_test_v1maxu_X1 \
+ insn_test_v1minu_X0 \
+ insn_test_v1minu_X1 \
+ insn_test_v1mnz_X0 \
+ insn_test_v1mnz_X1 \
+ insn_test_v1multu_X0 \
+ insn_test_v1mulu_X0 \
+ insn_test_v1mulus_X0 \
+ insn_test_v1mz_X0 \
+ insn_test_v1mz_X1 \
+ insn_test_v1sadau_X0 \
+ insn_test_v1sadu_X0 \
+ insn_test_v1shl_X0 \
+ insn_test_v1shl_X1 \
+ insn_test_v1shli_X0 \
+ insn_test_v1shli_X1 \
+ insn_test_v1shrs_X0 \
+ insn_test_v1shrs_X1 \
+ insn_test_v1shrsi_X0 \
+ insn_test_v1shrsi_X1 \
+ insn_test_v1shru_X0 \
+ insn_test_v1shru_X1 \
+ insn_test_v1shrui_X0 \
+ insn_test_v1shrui_X1 \
+ insn_test_v1sub_X0 \
+ insn_test_v1sub_X1 \
+ insn_test_v1subuc_X0 \
+ insn_test_v1subuc_X1 \
+ insn_test_v2add_X0 \
+ insn_test_v2add_X1 \
+ insn_test_v2addsc_X0 \
+ insn_test_v2addsc_X1 \
+ insn_test_v2adiffs_X0 \
+ insn_test_v2avgs_X0 \
+ insn_test_v2cmpeq_X0 \
+ insn_test_v2cmpeq_X1 \
+ insn_test_v2cmpeqi_X0 \
+ insn_test_v2cmpeqi_X1 \
+ insn_test_v2cmples_X0 \
+ insn_test_v2cmples_X1 \
+ insn_test_v2cmpleu_X0 \
+ insn_test_v2cmpleu_X1 \
+ insn_test_v2cmplts_X0 \
+ insn_test_v2cmplts_X1 \
+ insn_test_v2cmpltsi_X0 \
+ insn_test_v2cmpltsi_X1 \
+ insn_test_v2cmpltu_X0 \
+ insn_test_v2cmpltu_X1 \
+ insn_test_v2cmpltui_X0 \
+ insn_test_v2cmpltui_X1 \
+ insn_test_v2cmpne_X0 \
+ insn_test_v2cmpne_X1 \
+ insn_test_v2dotp_X0 \
+ insn_test_v2dotpa_X0 \
+ insn_test_v2int_h_X0 \
+ insn_test_v2int_h_X1 \
+ insn_test_v2int_l_X0 \
+ insn_test_v2int_l_X1 \
+ insn_test_v2maxs_X0 \
+ insn_test_v2maxs_X1 \
+ insn_test_v2mins_X0 \
+ insn_test_v2mins_X1 \
+ insn_test_v2mnz_X0 \
+ insn_test_v2mnz_X1 \
+ insn_test_v2mulfsc_X0 \
+ insn_test_v2muls_X0 \
+ insn_test_v2mults_X0 \
+ insn_test_v2mz_X0 \
+ insn_test_v2mz_X1 \
+ insn_test_v2packh_X0 \
+ insn_test_v2packh_X1 \
+ insn_test_v2packl_X0 \
+ insn_test_v2packl_X1 \
+ insn_test_v2packuc_X0 \
+ insn_test_v2packuc_X1 \
+ insn_test_v2sadas_X0 \
+ insn_test_v2sadau_X0 \
+ insn_test_v2sads_X0 \
+ insn_test_v2sadu_X0 \
+ insn_test_v2shl_X0 \
+ insn_test_v2shl_X1 \
+ insn_test_v2shli_X0 \
+ insn_test_v2shli_X1 \
+ insn_test_v2shlsc_X0 \
+ insn_test_v2shlsc_X1 \
+ insn_test_v2shrs_X0 \
+ insn_test_v2shrs_X1 \
+ insn_test_v2shrsi_X0 \
+ insn_test_v2shrsi_X1 \
+ insn_test_v2shru_X0 \
+ insn_test_v2shru_X1 \
+ insn_test_v2shrui_X0 \
+ insn_test_v2shrui_X1 \
+ insn_test_v2sub_X0 \
+ insn_test_v2sub_X1 \
+ insn_test_v2subsc_X0 \
+ insn_test_v2subsc_X1 \
+ insn_test_v4add_X0 \
+ insn_test_v4add_X1 \
+ insn_test_v4addsc_X0 \
+ insn_test_v4addsc_X1 \
+ insn_test_v4int_h_X0 \
+ insn_test_v4int_h_X1 \
+ insn_test_v4int_l_X0 \
+ insn_test_v4int_l_X1 \
+ insn_test_v4packsc_X0 \
+ insn_test_v4packsc_X1 \
+ insn_test_v4shl_X0 \
+ insn_test_v4shl_X1 \
+ insn_test_v4shlsc_X0 \
+ insn_test_v4shlsc_X1 \
+ insn_test_v4shrs_X0 \
+ insn_test_v4shrs_X1 \
+ insn_test_v4shru_X0 \
+ insn_test_v4shru_X1 \
+ insn_test_v4sub_X0 \
+ insn_test_v4sub_X1 \
+ insn_test_v4subsc_X0 \
+ insn_test_v4subsc_X1 \
+ insn_test_wh64_X1 \
+ insn_test_xor_X0 \
+ insn_test_xor_X1 \
+ insn_test_xor_Y0 \
+ insn_test_xor_Y1 \
+ insn_test_xori_X0 \
+ insn_test_xori_X1
check_PROGRAMS = \
- allexec
+ allexec \
+ $(insn_tests)
-AM_CFLAGS += @FLAG_M64@
+AM_CFLAGS += @FLAG_M64@ -w
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+gen_insn_test_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ -I../../../VEX/priv
+gen_insn_test_LDADD = ../../../VEX/priv/tilegx_disasm.o
+
+$(addsuffix .c, $(insn_tests)) : gen_insn_test
+ @echo $@
+ ./gen_test.sh $@
+
+$(addsuffix .stdout.exp, $(insn_tests)) : $(insn_tests)
+ @echo "Generate $@"
+ ./$(basename $(basename $@)) > $@
+
+$(addsuffix .stderr.exp, $(insn_tests)) :
+ @echo "Generate $@"
+ touch $@
+
+$(addsuffix .vgtest, $(insn_tests)) :
+ @echo "Generate $@"
+ echo -e "prog: $(basename $@)\nvgopts: -q" > $@
+
+check-am : $(addsuffix .stdout.exp, $(insn_tests)) $(addsuffix .stderr.exp, $(insn_tests)) $(addsuffix .vgtest, $(insn_tests))
+
+clean-am :
+ @rm -f *.stderr.exp *.stdout.exp *.vgtest $(addsuffix .c, $(insn_tests)) $(addsuffix .o, $(insn_tests)) $(insn_tests)
+ @rm -f *.o $(bin_PROGRAMS)
+
--- /dev/null
+//gcc a.c ../../../VEX/priv/tilegx_disasm.c -I ../../../ -I ../../../VEX/priv/ -I ../../../VEX/pub/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include "tilegx_disasm.h"
+
+#undef DGB
+
+static unsigned char op_abnorm[TILEGX_OPC_NONE] = {
+ /* Black list */
+ [ TILEGX_OPC_BPT ] = 1,
+ [ TILEGX_OPC_INFO ] = 1,
+ [ TILEGX_OPC_INFOL ] = 1,
+ [ TILEGX_OPC_DRAIN ] = 1,
+ [ TILEGX_OPC_IRET ] = 1,
+ [ TILEGX_OPC_SWINT0 ] = 1,
+ [ TILEGX_OPC_SWINT1 ] = 1,
+ [ TILEGX_OPC_SWINT2 ] = 1,
+ [ TILEGX_OPC_SWINT3 ] = 1,
+ [ TILEGX_OPC_LD4S_TLS ] = 1,
+ [ TILEGX_OPC_LD_TLS ] = 1,
+ [ TILEGX_OPC_MFSPR ] = 1,
+ [ TILEGX_OPC_MTSPR ] = 1,
+ [ TILEGX_OPC_ILL ] = 1,
+ [ TILEGX_OPC_NAP ] = 1,
+
+ /* mem load */
+ [ TILEGX_OPC_LD ] = 2,
+ [ TILEGX_OPC_LD_ADD ] = 2,
+ [ TILEGX_OPC_LD1S ] = 2,
+ [ TILEGX_OPC_LD1S_ADD ] = 2,
+ [ TILEGX_OPC_LD1U ] = 2,
+ [ TILEGX_OPC_LD1U_ADD ] = 2,
+ [ TILEGX_OPC_LD2S ] = 2,
+ [ TILEGX_OPC_LD2S_ADD ] = 2,
+ [ TILEGX_OPC_LD2U ] = 2,
+ [ TILEGX_OPC_LD2U_ADD ] = 2,
+ [ TILEGX_OPC_LD4S ] = 2,
+ [ TILEGX_OPC_LD4S_ADD ] = 2,
+ [ TILEGX_OPC_LD4U ] = 2,
+ [ TILEGX_OPC_LD4U_ADD ] = 2,
+ [ TILEGX_OPC_LDNA ] = 2,
+ [ TILEGX_OPC_LDNA_ADD ] = 2,
+ [ TILEGX_OPC_LDNT ] = 2,
+ [ TILEGX_OPC_LDNT1S ] = 2,
+ [ TILEGX_OPC_LDNT1S_ADD ] = 2,
+ [ TILEGX_OPC_LDNT1U ] = 2,
+ [ TILEGX_OPC_LDNT1U_ADD ] = 2,
+ [ TILEGX_OPC_LDNT2S ] = 2,
+ [ TILEGX_OPC_LDNT2S_ADD ] = 2,
+ [ TILEGX_OPC_LDNT2U ] = 2,
+ [ TILEGX_OPC_LDNT2U_ADD ] = 2,
+ [ TILEGX_OPC_LDNT4S ] = 2,
+ [ TILEGX_OPC_LDNT4S_ADD ] = 2,
+ [ TILEGX_OPC_LDNT4U ] = 2,
+ [ TILEGX_OPC_LDNT4U_ADD ] = 2,
+ [ TILEGX_OPC_LDNT_ADD ] = 2,
+
+ /* mem store */
+ [ TILEGX_OPC_ST ] = 4,
+ [ TILEGX_OPC_ST1 ] = 4,
+ [ TILEGX_OPC_ST1_ADD ] = 4,
+ [ TILEGX_OPC_ST2 ] = 4,
+ [ TILEGX_OPC_ST2_ADD ] = 4,
+ [ TILEGX_OPC_ST4 ] = 4,
+ [ TILEGX_OPC_ST4_ADD ] = 4,
+ [ TILEGX_OPC_ST_ADD ] = 4,
+ [ TILEGX_OPC_STNT ] = 4,
+ [ TILEGX_OPC_STNT1 ] = 4,
+ [ TILEGX_OPC_STNT1_ADD ] = 4,
+ [ TILEGX_OPC_STNT2 ] = 4,
+ [ TILEGX_OPC_STNT2_ADD ] = 4,
+ [ TILEGX_OPC_STNT4 ] = 4,
+ [ TILEGX_OPC_STNT4_ADD ] = 4,
+ [ TILEGX_OPC_STNT_ADD ] = 4,
+
+ /* conditional branch */
+ [ TILEGX_OPC_BEQZ ] = 8,
+ [ TILEGX_OPC_BEQZT ] = 8,
+ [ TILEGX_OPC_BGEZ ] = 8,
+ [ TILEGX_OPC_BGEZT ] = 8,
+ [ TILEGX_OPC_BGTZ ] = 8,
+ [ TILEGX_OPC_BGTZT ] = 8,
+ [ TILEGX_OPC_BLBC ] = 8,
+ [ TILEGX_OPC_BLBCT ] = 8,
+ [ TILEGX_OPC_BLBS ] = 8,
+ [ TILEGX_OPC_BLBST ] = 8,
+ [ TILEGX_OPC_BLEZ ] = 8,
+ [ TILEGX_OPC_BLEZT ] = 8,
+ [ TILEGX_OPC_BLTZ ] = 8,
+ [ TILEGX_OPC_BLTZT ] = 8,
+ [ TILEGX_OPC_BNEZ ] = 8,
+ [ TILEGX_OPC_BNEZT ] = 8,
+};
+
+
+static tilegx_bundle_bits
+encode_insn_tilegx_X (int p, struct tilegx_decoded_instruction decoded);
+
+static tilegx_bundle_bits
+encode_insn_tilegx_Y (int p, struct tilegx_decoded_instruction decoded);
+
+static int decode( tilegx_bundle_bits *p, int count, ULong pc );
+
+static uint64_t
+RAND(int round) {
+ static volatile uint64_t rand_seed = 0;
+ while (round-- > 0)
+ rand_seed = (rand_seed >> 8) * 201520052007 + 1971;
+#ifdef DBG
+ printf("RAND: %d\n", (int)rand_seed);
+#endif
+ return rand_seed;
+}
+
+
+int main(int argc, char* argv[])
+{
+ int i, start, end, pipe;
+ struct tilegx_decoded_instruction decoded;
+ if (argc == 1) {
+ pipe = 0x1F;
+ start = 0;
+ end = TILEGX_OPC_NONE;
+ } else if (argc == 3) {
+ start = atoi(argv[1]);
+
+ if (start >= TILEGX_OPC_NONE)
+ return -1;
+
+ end = start + 1;
+ /* pipes: X: bit 0,1; Y: bit 2-4 */
+ pipe = atoi(argv[2]);
+ } else {
+ return -1;
+ }
+
+ for (i = start; i < end; i++) {
+ memset(&decoded, 0, sizeof(decoded));
+ const struct tilegx_opcode *opcode = &tilegx_opcodes[i];
+ decoded.opcode = opcode;
+#ifdef DBG
+ const char *op_name = decoded.opcode->name;
+ printf("\n\n%d) %s\n", i, op_name);
+#endif
+
+ if (op_abnorm[i] & 1)
+ continue;
+
+ /* X0 pipeline */
+ if (tilegx_opcodes[i].pipes & 1 & pipe)
+ encode_insn_tilegx_X(0, decoded);
+
+ /* X1 pipeline */
+ if (tilegx_opcodes[i].pipes & 2 & pipe)
+ encode_insn_tilegx_X(1, decoded);
+
+ /* Y0 pipleline */
+ if (tilegx_opcodes[i].pipes & 4 & pipe)
+ encode_insn_tilegx_Y(0, decoded);
+
+ /* Y1 pipleline */
+ if (tilegx_opcodes[i].pipes & 8 & pipe)
+ encode_insn_tilegx_Y(1, decoded);
+
+ /* Y2 pipleline */
+ if (tilegx_opcodes[i].pipes & 16 & pipe)
+ encode_insn_tilegx_Y(2, decoded);
+ }
+
+ return 0;
+}
+
+static tilegx_bundle_bits
+encode_insn_tilegx_X(int p, struct tilegx_decoded_instruction decoded)
+{
+ const struct tilegx_opcode *opc =
+ decoded.opcode;
+ int op_idx = decoded.opcode->mnemonic;
+
+ tilegx_bundle_bits insn = 0;
+ //int pipeX01 = (opc->pipes & 0x01) ? 0 : 1;
+ int op_num = opc->num_operands;
+
+ /* Assume either X0 or X1. */
+ if ((opc->pipes & 3) == 0)
+ return -1;
+
+ /* Insert fnop in other pipe. */
+ insn = tilegx_opcodes[TILEGX_OPC_FNOP].
+ fixed_bit_values[p ? 0 : 1];
+#ifdef DBG
+ printf(" X%d, ", p);
+#endif
+
+ insn |= opc->fixed_bit_values[p];
+
+ printf("//file: _insn_test_%s_X%d.c\n", decoded.opcode->name, p);
+ printf("//op=%d\n", op_idx);
+ printf("#include <stdio.h>\n");
+ printf("#include <stdlib.h>\n");
+
+ printf("\n"
+ "void func_exit(void) {\n"
+ " printf(\"%cs\\n\", __func__);\n"
+ " exit(0);\n"
+ "}\n"
+ "\n"
+ "void func_call(void) {\n"
+ " printf(\"%cs\\n\", __func__);\n"
+ " exit(0);\n"
+ "}\n"
+ "\n"
+ "unsigned long mem[2] = { 0x%lx, 0x%lx };\n"
+ "\n", '%', '%', RAND(op_idx), RAND(op_idx));
+
+ printf("int main(void) {\n");
+ printf(" unsigned long a[4] = { 0, 0 };\n");
+
+ printf(" asm __volatile__ (\n");
+
+ int i, n = 0;
+
+ if (op_abnorm[op_idx] & 6)
+ {
+ /* loop for each operand. */
+ for (i = 0 ; i < op_num; i++)
+ {
+ const struct tilegx_operand *opd =
+ &tilegx_operands[opc->operands[p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand, pick register 0-50 randomly. */
+ decoded.operand_values[i] = RAND(op_idx) % 51;
+ int r = decoded.operand_values[i];
+ int64_t d = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
+#endif
+ int k = 0;
+ for (k = 3; k >= 0 ; k--) {
+ if (d >> (16 * k) || k == 0) {
+ printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
+ for (k--; k >= 0; k--)
+ printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
+ break;
+ }
+ }
+ } else {
+ /* An immediate operand, pick a random value. */
+ decoded.operand_values[i] = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
+#endif
+ }
+
+ Long op = decoded.operand_values[i];
+ decoded.operands[i] = opd;
+ ULong x = opd->insert(op);
+ insn |= x;
+ }
+ printf(" \"");
+ if (op_abnorm[op_idx] & 2)
+ printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[1], '%');
+ else
+ printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[0], '%');
+
+ printf(" \"");
+ decode(&insn, 2, 0);
+ printf("\\n\"\n");
+
+ /* loop for each operand. */
+ n = 0;
+ for (i = 0 ; i < op_num; i++)
+ {
+ const struct tilegx_operand *opd =
+ &tilegx_operands[opc->operands[p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand */
+ printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
+ n++;
+ }
+ }
+
+ printf(" ");
+ if (n)
+ printf(":");
+ for (i = 0; i < n; i++)
+ {
+ printf("\"=r\"(a[%d])", i);
+ if (i != n - 1)
+ printf(",");
+ }
+ printf(" : \"r\"(mem)");
+
+ printf(");\n");
+
+ printf(" printf(\"%c016lx %c016lx\\n\", mem[0], mem[1]);\n", '%', '%');
+
+ }
+ else if (op_idx == TILEGX_OPC_J)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"i\"(func_exit));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JAL)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"i\"(func_call));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JR || op_idx == TILEGX_OPC_JRP)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"r\"(func_exit));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JALR || op_idx == TILEGX_OPC_JALRP )
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"r\"(func_call));\n");
+ }
+ else if (op_abnorm[op_idx] & 8)
+ {
+ // OPC_BXXX conditional branch
+ int r = RAND(op_idx) % 51;
+ int d = RAND(op_idx) & 1;
+ printf(" \"movei r%d, %d\\n\"\n", r, d);
+ printf(" \"%s r%d, %c0\\n\"\n", decoded.opcode->name, r, '%');
+ printf(" \"jal %c1\\n\"\n", '%');
+ printf(" :: \"i\"(func_exit), \"i\"(func_call));\n");
+ }
+ else
+ {
+ /* loop for each operand. */
+ for (i = 0 ; i < op_num; i++)
+ {
+ const struct tilegx_operand *opd =
+ &tilegx_operands[opc->operands[p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand, pick register 0-50 randomly. */
+ decoded.operand_values[i] = RAND(op_idx) % 51;
+ int r = decoded.operand_values[i];
+ int64_t d = RAND(op_idx);
+
+#ifdef DBG
+ printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
+#endif
+ int k = 0;
+ for (k = 3; k >= 0 ; k--) {
+ if (d >> (16 * k) || k == 0) {
+ printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
+ for (k--; k >= 0; k--)
+ printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
+ break;
+ }
+ }
+ } else {
+ /* An immediate operand, pick a random value. */
+ decoded.operand_values[i] = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
+#endif
+ }
+
+ Long op = decoded.operand_values[i];
+ decoded.operands[i] = opd;
+ ULong x = opd->insert(op);
+ insn |= x;
+ }
+ printf(" \"");
+ decode(&insn, 2, 0);
+ printf("\\n\"\n");
+
+ /* loop for each operand. */
+ n = 0;
+ for (i = 0 ; i < op_num; i++)
+ {
+ const struct tilegx_operand *opd =
+ &tilegx_operands[opc->operands[p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand */
+ printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
+ n++;
+ }
+ }
+
+ printf(" ");
+ if (n)
+ printf(":");
+ for (i = 0; i < n; i++)
+ {
+ printf("\"=r\"(a[%d])", i);
+ if (i != n - 1)
+ printf(",");
+ }
+
+ printf(");\n");
+ }
+
+ for (i = 0; i < n; i++)
+ {
+ printf(" printf(\"%c016lx\\n\", a[%d]);\n", '%', i);
+ }
+ printf(" return 0;\n");
+ printf("}\n");
+ return insn;
+}
+
+static tilegx_bundle_bits
+encode_insn_tilegx_Y (int p, struct tilegx_decoded_instruction decoded )
+{
+ int i;
+ const struct tilegx_opcode *opc =
+ decoded.opcode;
+ int op_idx = decoded.opcode->mnemonic;
+
+ const struct tilegx_operand *opd;
+
+ tilegx_bundle_bits insn = 0;
+ Int op_num = opc->num_operands;
+
+ /* Insert fnop in Y0 and Y1 pipeline. */
+ if (p != 0)
+ insn |= tilegx_opcodes[TILEGX_OPC_FNOP].
+ fixed_bit_values[2];
+
+ if (p != 1)
+ insn |= tilegx_opcodes[TILEGX_OPC_FNOP].
+ fixed_bit_values[3];
+
+ /* Fill-in Y2 as dumy load "ld zero, sp" */
+ if (p != 2) {
+ insn |= tilegx_opcodes[TILEGX_OPC_LD].
+ fixed_bit_values[4];
+ opd = &tilegx_operands[tilegx_opcodes[TILEGX_OPC_LD].operands[4][0]];
+ insn |= opd->insert(63);
+ opd = &tilegx_operands[tilegx_opcodes[TILEGX_OPC_LD].operands[4][1]];
+ insn |= opd->insert(54);
+ }
+#ifdef DBG
+ printf(" Y%d, ", p);
+#endif
+
+ insn |= opc->fixed_bit_values[2 + p];
+
+ printf("//file: _insn_test_%s_Y%d.c\n", decoded.opcode->name, p);
+ printf("//op=%d\n", op_idx);
+ printf("#include <stdio.h>\n");
+ printf("#include <stdlib.h>\n");
+
+ printf("\n"
+ "void func_exit(void) {\n"
+ " printf(\"%cs\\n\", __func__);\n"
+ " exit(0);\n"
+ "}\n"
+ "\n"
+ "void func_call(void) {\n"
+ " printf(\"%cs\\n\", __func__);\n"
+ " exit(0);\n"
+ "}\n"
+ "\n"
+ "unsigned long mem[2] = { 0x%lx, 0x%lx };\n"
+ "\n", '%', '%', RAND(op_idx), RAND(op_idx));
+
+ printf("int main(void) {\n");
+ printf(" unsigned long a[4] = { 0, 0 };\n");
+
+ printf(" asm __volatile__ (\n");
+
+ int n = 0;
+
+ if (op_abnorm[op_idx] & 6)
+ {
+ /* loop for each operand. */
+ for (i = 0 ; i < op_num; i++)
+ {
+ opd = &tilegx_operands[opc->operands[2 + p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand, pick register 0-53 randomly. */
+ decoded.operand_values[i] = RAND(op_idx) % 53;
+ int r = decoded.operand_values[i];
+ int64_t d = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
+#endif
+ int k = 0;
+ for (k = 3; k >= 0 ; k--) {
+ if (d >> (16 * k) || k == 0) {
+ printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
+ for (k--; k >= 0; k--)
+ printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
+ break;
+ }
+ }
+ } else {
+ /* An immediate operand, pick a random value. */
+ decoded.operand_values[i] = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
+#endif
+ }
+
+ Long op = decoded.operand_values[i];
+ decoded.operands[i] = opd;
+ ULong x = opd->insert(op);
+ insn |= x;
+ }
+ printf(" \"");
+ if (op_abnorm[op_idx] & 2)
+ printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[1], '%');
+ else
+ printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[0], '%');
+
+ printf(" \"");
+ decode(&insn, 3, 0);
+ printf("\\n\"\n");
+
+ /* loop for each operand. */
+ n = 0;
+ for (i = 0 ; i < op_num; i++)
+ {
+ opd = &tilegx_operands[opc->operands[2 + p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand */
+ printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
+ n++;
+ }
+ }
+
+ printf(" ");
+ if (n)
+ printf(":");
+ for (i = 0; i < n; i++)
+ {
+ printf("\"=r\"(a[%d])", i);
+ if (i != n - 1)
+ printf(",");
+ }
+ printf(" : \"r\"(mem)");
+
+ printf(");\n");
+
+ printf(" printf(\"%c016lx %c016lx\\n\", mem[0], mem[1]);\n", '%', '%');
+
+ }
+ else if (op_idx == TILEGX_OPC_J)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"i\"(func_exit));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JAL)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"i\"(func_call));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JR || op_idx == TILEGX_OPC_JRP)
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"r\"(func_exit));\n");
+ }
+ else if (op_idx == TILEGX_OPC_JALR || op_idx == TILEGX_OPC_JALRP )
+ {
+ printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
+ printf(" :: \"r\"(func_call));\n");
+ }
+ else if (op_abnorm[op_idx] & 8)
+ {
+ // OPC_BXXX conditional branch
+ int r = RAND(op_idx) % 51;
+ int d = RAND(op_idx) & 1;
+ printf(" \"movei r%d, %d\\n\"\n", r, d);
+ printf(" \"%s r%d, %c0\\n\"\n", decoded.opcode->name, r, '%');
+ printf(" \"jal %c1\\n\"\n", '%');
+ printf(" :: \"i\"(func_exit), \"i\"(func_call));\n");
+ }
+ else
+ {
+ /* loop for each operand. */
+ for (i = 0 ; i < op_num; i++)
+ {
+ opd = &tilegx_operands[opc->operands[2 + p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand, pick register 0-50 randomly. */
+ decoded.operand_values[i] = RAND(op_idx) % 51;
+ int r = decoded.operand_values[i];
+ int64_t d = RAND(op_idx);
+
+#ifdef DBG
+ printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
+#endif
+ int k = 0;
+ for (k = 3; k >= 0 ; k--) {
+ if (d >> (16 * k) || k == 0) {
+ printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
+ for (k--; k >= 0; k--)
+ printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
+ break;
+ }
+ }
+ } else {
+ /* An immediate operand, pick a random value. */
+ decoded.operand_values[i] = RAND(op_idx);
+#ifdef DBG
+ printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
+#endif
+ }
+
+ Long op = decoded.operand_values[i];
+ decoded.operands[i] = opd;
+ ULong x = opd->insert(op);
+ insn |= x;
+ }
+ printf(" \"");
+ decode(&insn, 3, 0);
+ printf("\\n\"\n");
+
+ /* loop for each operand. */
+ n = 0;
+ for (i = 0 ; i < op_num; i++)
+ {
+ opd = &tilegx_operands[opc->operands[2 + p][i]];
+
+ if (opd->type == TILEGX_OP_TYPE_REGISTER) {
+ /* A register operand */
+ printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
+ n++;
+ }
+ }
+
+ printf(" ");
+ if (n)
+ printf(":");
+ for (i = 0; i < n; i++)
+ {
+ printf("\"=r\"(a[%d])", i);
+ if (i != n - 1)
+ printf(",");
+ }
+
+ printf(");\n");
+ }
+
+ for (i = 0; i < n; i++)
+ {
+ printf(" printf(\"%c016lx\\n\", a[%d]);\n", '%', i);
+ }
+ printf(" return 0;\n");
+ printf("}\n");
+ return insn;
+}
+
+static int display_insn ( struct tilegx_decoded_instruction
+ decoded[1] )
+{
+ int i;
+ for (i = 0;
+ decoded[i].opcode && (i < 1);
+ i++) {
+ int n;
+ printf("%s ", decoded[i].opcode->name);
+
+ for (n = 0; n < decoded[i].opcode->num_operands; n++) {
+ const struct tilegx_operand *op = decoded[i].operands[n];
+
+ if (op->type == TILEGX_OP_TYPE_REGISTER)
+ printf("r%d", (int) decoded[i].operand_values[n]);
+ else
+ printf("%ld", (unsigned long)decoded[i].operand_values[n]);
+
+ if (n != (decoded[i].opcode->num_operands - 1))
+ printf(", ");
+ }
+ printf(" ");
+ }
+ return i;
+}
+
+int decode( tilegx_bundle_bits *p, int count, ULong pc )
+{
+ struct tilegx_decoded_instruction
+ decode[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
+
+ if (pc) {
+ printf("%012llx %016llx ", pc, (ULong)p[0]);
+ pc += 8;
+ }
+ parse_insn_tilegx(p[0], 0, decode);
+
+ int k;
+
+ printf("{ ");
+
+ for(k = 0; decode[k].opcode && (k <TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE);
+ k++) {
+
+ display_insn(&decode[k]);
+ if (--count > 0)
+ printf("; ");
+ }
+
+ printf(" }");
+
+ return count;
+}
--- /dev/null
+#!/bin/bash
+
+FILES=( "5 1 insn_test_move_X0.c"
+ "5 2 insn_test_move_X1.c"
+ "5 4 insn_test_move_Y0.c"
+ "5 8 insn_test_move_Y1.c"
+ "6 1 insn_test_movei_X0.c"
+ "6 2 insn_test_movei_X1.c"
+ "6 4 insn_test_movei_Y0.c"
+ "6 8 insn_test_movei_Y1.c"
+ "7 1 insn_test_moveli_X0.c"
+ "7 2 insn_test_moveli_X1.c"
+ "8 2 insn_test_prefetch_X1.c"
+ "8 16 insn_test_prefetch_Y2.c"
+ "9 2 insn_test_prefetch_add_l1_X1.c"
+ "10 2 insn_test_prefetch_add_l1_fault_X1.c"
+ "11 2 insn_test_prefetch_add_l2_X1.c"
+ "12 2 insn_test_prefetch_add_l2_fault_X1.c"
+ "13 2 insn_test_prefetch_add_l3_X1.c"
+ "14 2 insn_test_prefetch_add_l3_fault_X1.c"
+ "15 2 insn_test_prefetch_l1_X1.c"
+ "15 16 insn_test_prefetch_l1_Y2.c"
+ "16 2 insn_test_prefetch_l1_fault_X1.c"
+ "16 16 insn_test_prefetch_l1_fault_Y2.c"
+ "17 2 insn_test_prefetch_l2_X1.c"
+ "17 16 insn_test_prefetch_l2_Y2.c"
+ "18 2 insn_test_prefetch_l2_fault_X1.c"
+ "18 16 insn_test_prefetch_l2_fault_Y2.c"
+ "19 2 insn_test_prefetch_l3_X1.c"
+ "19 16 insn_test_prefetch_l3_Y2.c"
+ "20 2 insn_test_prefetch_l3_fault_X1.c"
+ "20 16 insn_test_prefetch_l3_fault_Y2.c"
+ "21 2 insn_test_raise_X1.c"
+ "22 1 insn_test_add_X0.c"
+ "22 2 insn_test_add_X1.c"
+ "22 4 insn_test_add_Y0.c"
+ "22 8 insn_test_add_Y1.c"
+ "23 1 insn_test_addi_X0.c"
+ "23 2 insn_test_addi_X1.c"
+ "23 4 insn_test_addi_Y0.c"
+ "23 8 insn_test_addi_Y1.c"
+ "24 1 insn_test_addli_X0.c"
+ "24 2 insn_test_addli_X1.c"
+ "25 1 insn_test_addx_X0.c"
+ "25 2 insn_test_addx_X1.c"
+ "25 4 insn_test_addx_Y0.c"
+ "25 8 insn_test_addx_Y1.c"
+ "26 1 insn_test_addxi_X0.c"
+ "26 2 insn_test_addxi_X1.c"
+ "26 4 insn_test_addxi_Y0.c"
+ "26 8 insn_test_addxi_Y1.c"
+ "27 1 insn_test_addxli_X0.c"
+ "27 2 insn_test_addxli_X1.c"
+ "28 1 insn_test_addxsc_X0.c"
+ "28 2 insn_test_addxsc_X1.c"
+ "29 1 insn_test_and_X0.c"
+ "29 2 insn_test_and_X1.c"
+ "29 4 insn_test_and_Y0.c"
+ "29 8 insn_test_and_Y1.c"
+ "30 1 insn_test_andi_X0.c"
+ "30 2 insn_test_andi_X1.c"
+ "30 4 insn_test_andi_Y0.c"
+ "30 8 insn_test_andi_Y1.c"
+ "31 2 insn_test_beqz_X1.c"
+ "32 2 insn_test_beqzt_X1.c"
+ "33 1 insn_test_bfexts_X0.c"
+ "34 1 insn_test_bfextu_X0.c"
+ "35 1 insn_test_bfins_X0.c"
+ "36 2 insn_test_bgez_X1.c"
+ "37 2 insn_test_bgezt_X1.c"
+ "38 2 insn_test_bgtz_X1.c"
+ "39 2 insn_test_bgtzt_X1.c"
+ "40 2 insn_test_blbc_X1.c"
+ "41 2 insn_test_blbct_X1.c"
+ "42 2 insn_test_blbs_X1.c"
+ "43 2 insn_test_blbst_X1.c"
+ "44 2 insn_test_blez_X1.c"
+ "45 2 insn_test_blezt_X1.c"
+ "46 2 insn_test_bltz_X1.c"
+ "47 2 insn_test_bltzt_X1.c"
+ "48 2 insn_test_bnez_X1.c"
+ "49 2 insn_test_bnezt_X1.c"
+ "50 1 insn_test_clz_X0.c"
+ "50 4 insn_test_clz_Y0.c"
+ "51 1 insn_test_cmoveqz_X0.c"
+ "51 4 insn_test_cmoveqz_Y0.c"
+ "52 1 insn_test_cmovnez_X0.c"
+ "52 4 insn_test_cmovnez_Y0.c"
+ "53 1 insn_test_cmpeq_X0.c"
+ "53 2 insn_test_cmpeq_X1.c"
+ "53 4 insn_test_cmpeq_Y0.c"
+ "53 8 insn_test_cmpeq_Y1.c"
+ "54 1 insn_test_cmpeqi_X0.c"
+ "54 2 insn_test_cmpeqi_X1.c"
+ "54 4 insn_test_cmpeqi_Y0.c"
+ "54 8 insn_test_cmpeqi_Y1.c"
+ "55 2 insn_test_cmpexch_X1.c"
+ "56 2 insn_test_cmpexch4_X1.c"
+ "57 1 insn_test_cmples_X0.c"
+ "57 2 insn_test_cmples_X1.c"
+ "57 4 insn_test_cmples_Y0.c"
+ "57 8 insn_test_cmples_Y1.c"
+ "58 1 insn_test_cmpleu_X0.c"
+ "58 2 insn_test_cmpleu_X1.c"
+ "58 4 insn_test_cmpleu_Y0.c"
+ "58 8 insn_test_cmpleu_Y1.c"
+ "59 1 insn_test_cmplts_X0.c"
+ "59 2 insn_test_cmplts_X1.c"
+ "59 4 insn_test_cmplts_Y0.c"
+ "59 8 insn_test_cmplts_Y1.c"
+ "60 1 insn_test_cmpltsi_X0.c"
+ "60 2 insn_test_cmpltsi_X1.c"
+ "60 4 insn_test_cmpltsi_Y0.c"
+ "60 8 insn_test_cmpltsi_Y1.c"
+ "61 1 insn_test_cmpltu_X0.c"
+ "61 2 insn_test_cmpltu_X1.c"
+ "61 4 insn_test_cmpltu_Y0.c"
+ "61 8 insn_test_cmpltu_Y1.c"
+ "62 1 insn_test_cmpltui_X0.c"
+ "62 2 insn_test_cmpltui_X1.c"
+ "63 1 insn_test_cmpne_X0.c"
+ "63 2 insn_test_cmpne_X1.c"
+ "63 4 insn_test_cmpne_Y0.c"
+ "63 8 insn_test_cmpne_Y1.c"
+ "64 1 insn_test_cmul_X0.c"
+ "65 1 insn_test_cmula_X0.c"
+ "66 1 insn_test_cmulaf_X0.c"
+ "67 1 insn_test_cmulf_X0.c"
+ "68 1 insn_test_cmulfr_X0.c"
+ "69 1 insn_test_cmulh_X0.c"
+ "70 1 insn_test_cmulhr_X0.c"
+ "71 1 insn_test_crc32_32_X0.c"
+ "72 1 insn_test_crc32_8_X0.c"
+ "73 1 insn_test_ctz_X0.c"
+ "73 4 insn_test_ctz_Y0.c"
+ "74 1 insn_test_dblalign_X0.c"
+ "75 1 insn_test_dblalign2_X0.c"
+ "75 2 insn_test_dblalign2_X1.c"
+ "76 1 insn_test_dblalign4_X0.c"
+ "76 2 insn_test_dblalign4_X1.c"
+ "77 1 insn_test_dblalign6_X0.c"
+ "77 2 insn_test_dblalign6_X1.c"
+ "79 2 insn_test_dtlbpr_X1.c"
+ "80 2 insn_test_exch_X1.c"
+ "81 2 insn_test_exch4_X1.c"
+ "82 1 insn_test_fdouble_add_flags_X0.c"
+ "83 1 insn_test_fdouble_addsub_X0.c"
+ "84 1 insn_test_fdouble_mul_flags_X0.c"
+ "85 1 insn_test_fdouble_pack1_X0.c"
+ "86 1 insn_test_fdouble_pack2_X0.c"
+ "87 1 insn_test_fdouble_sub_flags_X0.c"
+ "88 1 insn_test_fdouble_unpack_max_X0.c"
+ "89 1 insn_test_fdouble_unpack_min_X0.c"
+ "90 2 insn_test_fetchadd_X1.c"
+ "91 2 insn_test_fetchadd4_X1.c"
+ "92 2 insn_test_fetchaddgez_X1.c"
+ "93 2 insn_test_fetchaddgez4_X1.c"
+ "94 2 insn_test_fetchand_X1.c"
+ "95 2 insn_test_fetchand4_X1.c"
+ "96 2 insn_test_fetchor_X1.c"
+ "97 2 insn_test_fetchor4_X1.c"
+ "98 2 insn_test_finv_X1.c"
+ "99 2 insn_test_flush_X1.c"
+ "100 2 insn_test_flushwb_X1.c"
+ "101 1 insn_test_fnop_X0.c"
+ "101 2 insn_test_fnop_X1.c"
+ "101 4 insn_test_fnop_Y0.c"
+ "101 8 insn_test_fnop_Y1.c"
+ "102 1 insn_test_fsingle_add1_X0.c"
+ "103 1 insn_test_fsingle_addsub2_X0.c"
+ "104 1 insn_test_fsingle_mul1_X0.c"
+ "105 1 insn_test_fsingle_mul2_X0.c"
+ "106 1 insn_test_fsingle_pack1_X0.c"
+ "106 4 insn_test_fsingle_pack1_Y0.c"
+ "107 1 insn_test_fsingle_pack2_X0.c"
+ "108 1 insn_test_fsingle_sub1_X0.c"
+ "109 2 insn_test_icoh_X1.c"
+ "111 2 insn_test_inv_X1.c"
+ "113 2 insn_test_j_X1.c"
+ "114 2 insn_test_jal_X1.c"
+ "115 2 insn_test_jalr_X1.c"
+ "115 8 insn_test_jalr_Y1.c"
+ "116 2 insn_test_jalrp_X1.c"
+ "116 8 insn_test_jalrp_Y1.c"
+ "117 2 insn_test_jr_X1.c"
+ "117 8 insn_test_jr_Y1.c"
+ "118 2 insn_test_jrp_X1.c"
+ "118 8 insn_test_jrp_Y1.c"
+ "119 2 insn_test_ld_X1.c"
+ "119 16 insn_test_ld_Y2.c"
+ "120 2 insn_test_ld1s_X1.c"
+ "120 16 insn_test_ld1s_Y2.c"
+ "121 2 insn_test_ld1s_add_X1.c"
+ "122 2 insn_test_ld1u_X1.c"
+ "122 16 insn_test_ld1u_Y2.c"
+ "123 2 insn_test_ld1u_add_X1.c"
+ "124 2 insn_test_ld2s_X1.c"
+ "124 16 insn_test_ld2s_Y2.c"
+ "125 2 insn_test_ld2s_add_X1.c"
+ "126 2 insn_test_ld2u_X1.c"
+ "126 16 insn_test_ld2u_Y2.c"
+ "127 2 insn_test_ld2u_add_X1.c"
+ "128 2 insn_test_ld4s_X1.c"
+ "128 16 insn_test_ld4s_Y2.c"
+ "129 2 insn_test_ld4s_add_X1.c"
+ "130 2 insn_test_ld4u_X1.c"
+ "130 16 insn_test_ld4u_Y2.c"
+ "131 2 insn_test_ld4u_add_X1.c"
+ "132 2 insn_test_ld_add_X1.c"
+ "133 2 insn_test_ldna_X1.c"
+ "134 2 insn_test_ldna_add_X1.c"
+ "135 2 insn_test_ldnt_X1.c"
+ "136 2 insn_test_ldnt1s_X1.c"
+ "137 2 insn_test_ldnt1s_add_X1.c"
+ "138 2 insn_test_ldnt1u_X1.c"
+ "139 2 insn_test_ldnt1u_add_X1.c"
+ "140 2 insn_test_ldnt2s_X1.c"
+ "141 2 insn_test_ldnt2s_add_X1.c"
+ "142 2 insn_test_ldnt2u_X1.c"
+ "143 2 insn_test_ldnt2u_add_X1.c"
+ "144 2 insn_test_ldnt4s_X1.c"
+ "145 2 insn_test_ldnt4s_add_X1.c"
+ "146 2 insn_test_ldnt4u_X1.c"
+ "147 2 insn_test_ldnt4u_add_X1.c"
+ "148 2 insn_test_ldnt_add_X1.c"
+ "149 2 insn_test_lnk_X1.c"
+ "149 8 insn_test_lnk_Y1.c"
+ "150 2 insn_test_mf_X1.c"
+ "152 1 insn_test_mm_X0.c"
+ "153 1 insn_test_mnz_X0.c"
+ "153 2 insn_test_mnz_X1.c"
+ "153 4 insn_test_mnz_Y0.c"
+ "153 8 insn_test_mnz_Y1.c"
+ "155 1 insn_test_mul_hs_hs_X0.c"
+ "155 4 insn_test_mul_hs_hs_Y0.c"
+ "156 1 insn_test_mul_hs_hu_X0.c"
+ "157 1 insn_test_mul_hs_ls_X0.c"
+ "158 1 insn_test_mul_hs_lu_X0.c"
+ "159 1 insn_test_mul_hu_hu_X0.c"
+ "159 4 insn_test_mul_hu_hu_Y0.c"
+ "160 1 insn_test_mul_hu_ls_X0.c"
+ "161 1 insn_test_mul_hu_lu_X0.c"
+ "162 1 insn_test_mul_ls_ls_X0.c"
+ "162 4 insn_test_mul_ls_ls_Y0.c"
+ "163 1 insn_test_mul_ls_lu_X0.c"
+ "164 1 insn_test_mul_lu_lu_X0.c"
+ "164 4 insn_test_mul_lu_lu_Y0.c"
+ "165 1 insn_test_mula_hs_hs_X0.c"
+ "165 4 insn_test_mula_hs_hs_Y0.c"
+ "166 1 insn_test_mula_hs_hu_X0.c"
+ "167 1 insn_test_mula_hs_ls_X0.c"
+ "168 1 insn_test_mula_hs_lu_X0.c"
+ "169 1 insn_test_mula_hu_hu_X0.c"
+ "169 4 insn_test_mula_hu_hu_Y0.c"
+ "170 1 insn_test_mula_hu_ls_X0.c"
+ "171 1 insn_test_mula_hu_lu_X0.c"
+ "172 1 insn_test_mula_ls_ls_X0.c"
+ "172 4 insn_test_mula_ls_ls_Y0.c"
+ "173 1 insn_test_mula_ls_lu_X0.c"
+ "174 1 insn_test_mula_lu_lu_X0.c"
+ "174 4 insn_test_mula_lu_lu_Y0.c"
+ "175 1 insn_test_mulax_X0.c"
+ "175 4 insn_test_mulax_Y0.c"
+ "176 1 insn_test_mulx_X0.c"
+ "176 4 insn_test_mulx_Y0.c"
+ "177 1 insn_test_mz_X0.c"
+ "177 2 insn_test_mz_X1.c"
+ "177 4 insn_test_mz_Y0.c"
+ "177 8 insn_test_mz_Y1.c"
+ "179 1 insn_test_nop_X0.c"
+ "179 2 insn_test_nop_X1.c"
+ "179 4 insn_test_nop_Y0.c"
+ "179 8 insn_test_nop_Y1.c"
+ "180 1 insn_test_nor_X0.c"
+ "180 2 insn_test_nor_X1.c"
+ "180 4 insn_test_nor_Y0.c"
+ "180 8 insn_test_nor_Y1.c"
+ "181 1 insn_test_or_X0.c"
+ "181 2 insn_test_or_X1.c"
+ "181 4 insn_test_or_Y0.c"
+ "181 8 insn_test_or_Y1.c"
+ "182 1 insn_test_ori_X0.c"
+ "182 2 insn_test_ori_X1.c"
+ "183 1 insn_test_pcnt_X0.c"
+ "183 4 insn_test_pcnt_Y0.c"
+ "184 1 insn_test_revbits_X0.c"
+ "184 4 insn_test_revbits_Y0.c"
+ "185 1 insn_test_revbytes_X0.c"
+ "185 4 insn_test_revbytes_Y0.c"
+ "186 1 insn_test_rotl_X0.c"
+ "186 2 insn_test_rotl_X1.c"
+ "186 4 insn_test_rotl_Y0.c"
+ "186 8 insn_test_rotl_Y1.c"
+ "187 1 insn_test_rotli_X0.c"
+ "187 2 insn_test_rotli_X1.c"
+ "187 4 insn_test_rotli_Y0.c"
+ "187 8 insn_test_rotli_Y1.c"
+ "188 1 insn_test_shl_X0.c"
+ "188 2 insn_test_shl_X1.c"
+ "188 4 insn_test_shl_Y0.c"
+ "188 8 insn_test_shl_Y1.c"
+ "189 1 insn_test_shl16insli_X0.c"
+ "189 2 insn_test_shl16insli_X1.c"
+ "190 1 insn_test_shl1add_X0.c"
+ "190 2 insn_test_shl1add_X1.c"
+ "190 4 insn_test_shl1add_Y0.c"
+ "190 8 insn_test_shl1add_Y1.c"
+ "191 1 insn_test_shl1addx_X0.c"
+ "191 2 insn_test_shl1addx_X1.c"
+ "191 4 insn_test_shl1addx_Y0.c"
+ "191 8 insn_test_shl1addx_Y1.c"
+ "192 1 insn_test_shl2add_X0.c"
+ "192 2 insn_test_shl2add_X1.c"
+ "192 4 insn_test_shl2add_Y0.c"
+ "192 8 insn_test_shl2add_Y1.c"
+ "193 1 insn_test_shl2addx_X0.c"
+ "193 2 insn_test_shl2addx_X1.c"
+ "193 4 insn_test_shl2addx_Y0.c"
+ "193 8 insn_test_shl2addx_Y1.c"
+ "194 1 insn_test_shl3add_X0.c"
+ "194 2 insn_test_shl3add_X1.c"
+ "194 4 insn_test_shl3add_Y0.c"
+ "194 8 insn_test_shl3add_Y1.c"
+ "195 1 insn_test_shl3addx_X0.c"
+ "195 2 insn_test_shl3addx_X1.c"
+ "195 4 insn_test_shl3addx_Y0.c"
+ "195 8 insn_test_shl3addx_Y1.c"
+ "196 1 insn_test_shli_X0.c"
+ "196 2 insn_test_shli_X1.c"
+ "196 4 insn_test_shli_Y0.c"
+ "196 8 insn_test_shli_Y1.c"
+ "197 1 insn_test_shlx_X0.c"
+ "197 2 insn_test_shlx_X1.c"
+ "198 1 insn_test_shlxi_X0.c"
+ "198 2 insn_test_shlxi_X1.c"
+ "199 1 insn_test_shrs_X0.c"
+ "199 2 insn_test_shrs_X1.c"
+ "199 4 insn_test_shrs_Y0.c"
+ "199 8 insn_test_shrs_Y1.c"
+ "200 1 insn_test_shrsi_X0.c"
+ "200 2 insn_test_shrsi_X1.c"
+ "200 4 insn_test_shrsi_Y0.c"
+ "200 8 insn_test_shrsi_Y1.c"
+ "201 1 insn_test_shru_X0.c"
+ "201 2 insn_test_shru_X1.c"
+ "201 4 insn_test_shru_Y0.c"
+ "201 8 insn_test_shru_Y1.c"
+ "202 1 insn_test_shrui_X0.c"
+ "202 2 insn_test_shrui_X1.c"
+ "202 4 insn_test_shrui_Y0.c"
+ "202 8 insn_test_shrui_Y1.c"
+ "203 1 insn_test_shrux_X0.c"
+ "203 2 insn_test_shrux_X1.c"
+ "204 1 insn_test_shruxi_X0.c"
+ "204 2 insn_test_shruxi_X1.c"
+ "205 1 insn_test_shufflebytes_X0.c"
+ "206 2 insn_test_st_X1.c"
+ "206 16 insn_test_st_Y2.c"
+ "207 2 insn_test_st1_X1.c"
+ "207 16 insn_test_st1_Y2.c"
+ "208 2 insn_test_st1_add_X1.c"
+ "209 2 insn_test_st2_X1.c"
+ "209 16 insn_test_st2_Y2.c"
+ "210 2 insn_test_st2_add_X1.c"
+ "211 2 insn_test_st4_X1.c"
+ "211 16 insn_test_st4_Y2.c"
+ "212 2 insn_test_st4_add_X1.c"
+ "213 2 insn_test_st_add_X1.c"
+ "214 2 insn_test_stnt_X1.c"
+ "215 2 insn_test_stnt1_X1.c"
+ "216 2 insn_test_stnt1_add_X1.c"
+ "217 2 insn_test_stnt2_X1.c"
+ "218 2 insn_test_stnt2_add_X1.c"
+ "219 2 insn_test_stnt4_X1.c"
+ "220 2 insn_test_stnt4_add_X1.c"
+ "221 2 insn_test_stnt_add_X1.c"
+ "222 1 insn_test_sub_X0.c"
+ "222 2 insn_test_sub_X1.c"
+ "222 4 insn_test_sub_Y0.c"
+ "222 8 insn_test_sub_Y1.c"
+ "223 1 insn_test_subx_X0.c"
+ "223 2 insn_test_subx_X1.c"
+ "223 4 insn_test_subx_Y0.c"
+ "223 8 insn_test_subx_Y1.c"
+ "224 1 insn_test_subxsc_X0.c"
+ "224 2 insn_test_subxsc_X1.c"
+ "229 1 insn_test_tblidxb0_X0.c"
+ "229 4 insn_test_tblidxb0_Y0.c"
+ "230 1 insn_test_tblidxb1_X0.c"
+ "230 4 insn_test_tblidxb1_Y0.c"
+ "231 1 insn_test_tblidxb2_X0.c"
+ "231 4 insn_test_tblidxb2_Y0.c"
+ "232 1 insn_test_tblidxb3_X0.c"
+ "232 4 insn_test_tblidxb3_Y0.c"
+ "233 1 insn_test_v1add_X0.c"
+ "233 2 insn_test_v1add_X1.c"
+ "234 1 insn_test_v1addi_X0.c"
+ "234 2 insn_test_v1addi_X1.c"
+ "235 1 insn_test_v1adduc_X0.c"
+ "235 2 insn_test_v1adduc_X1.c"
+ "236 1 insn_test_v1adiffu_X0.c"
+ "237 1 insn_test_v1avgu_X0.c"
+ "238 1 insn_test_v1cmpeq_X0.c"
+ "238 2 insn_test_v1cmpeq_X1.c"
+ "239 1 insn_test_v1cmpeqi_X0.c"
+ "239 2 insn_test_v1cmpeqi_X1.c"
+ "240 1 insn_test_v1cmples_X0.c"
+ "240 2 insn_test_v1cmples_X1.c"
+ "241 1 insn_test_v1cmpleu_X0.c"
+ "241 2 insn_test_v1cmpleu_X1.c"
+ "242 1 insn_test_v1cmplts_X0.c"
+ "242 2 insn_test_v1cmplts_X1.c"
+ "243 1 insn_test_v1cmpltsi_X0.c"
+ "243 2 insn_test_v1cmpltsi_X1.c"
+ "244 1 insn_test_v1cmpltu_X0.c"
+ "244 2 insn_test_v1cmpltu_X1.c"
+ "245 1 insn_test_v1cmpltui_X0.c"
+ "245 2 insn_test_v1cmpltui_X1.c"
+ "246 1 insn_test_v1cmpne_X0.c"
+ "246 2 insn_test_v1cmpne_X1.c"
+ "247 1 insn_test_v1ddotpu_X0.c"
+ "248 1 insn_test_v1ddotpua_X0.c"
+ "249 1 insn_test_v1ddotpus_X0.c"
+ "250 1 insn_test_v1ddotpusa_X0.c"
+ "251 1 insn_test_v1dotp_X0.c"
+ "252 1 insn_test_v1dotpa_X0.c"
+ "253 1 insn_test_v1dotpu_X0.c"
+ "254 1 insn_test_v1dotpua_X0.c"
+ "255 1 insn_test_v1dotpus_X0.c"
+ "256 1 insn_test_v1dotpusa_X0.c"
+ "257 1 insn_test_v1int_h_X0.c"
+ "257 2 insn_test_v1int_h_X1.c"
+ "258 1 insn_test_v1int_l_X0.c"
+ "258 2 insn_test_v1int_l_X1.c"
+ "259 1 insn_test_v1maxu_X0.c"
+ "259 2 insn_test_v1maxu_X1.c"
+ "260 1 insn_test_v1maxui_X0.c"
+ "260 2 insn_test_v1maxui_X1.c"
+ "261 1 insn_test_v1minu_X0.c"
+ "261 2 insn_test_v1minu_X1.c"
+ "262 1 insn_test_v1minui_X0.c"
+ "262 2 insn_test_v1minui_X1.c"
+ "263 1 insn_test_v1mnz_X0.c"
+ "263 2 insn_test_v1mnz_X1.c"
+ "264 1 insn_test_v1multu_X0.c"
+ "265 1 insn_test_v1mulu_X0.c"
+ "266 1 insn_test_v1mulus_X0.c"
+ "267 1 insn_test_v1mz_X0.c"
+ "267 2 insn_test_v1mz_X1.c"
+ "268 1 insn_test_v1sadau_X0.c"
+ "269 1 insn_test_v1sadu_X0.c"
+ "270 1 insn_test_v1shl_X0.c"
+ "270 2 insn_test_v1shl_X1.c"
+ "271 1 insn_test_v1shli_X0.c"
+ "271 2 insn_test_v1shli_X1.c"
+ "272 1 insn_test_v1shrs_X0.c"
+ "272 2 insn_test_v1shrs_X1.c"
+ "273 1 insn_test_v1shrsi_X0.c"
+ "273 2 insn_test_v1shrsi_X1.c"
+ "274 1 insn_test_v1shru_X0.c"
+ "274 2 insn_test_v1shru_X1.c"
+ "275 1 insn_test_v1shrui_X0.c"
+ "275 2 insn_test_v1shrui_X1.c"
+ "276 1 insn_test_v1sub_X0.c"
+ "276 2 insn_test_v1sub_X1.c"
+ "277 1 insn_test_v1subuc_X0.c"
+ "277 2 insn_test_v1subuc_X1.c"
+ "278 1 insn_test_v2add_X0.c"
+ "278 2 insn_test_v2add_X1.c"
+ "279 1 insn_test_v2addi_X0.c"
+ "279 2 insn_test_v2addi_X1.c"
+ "280 1 insn_test_v2addsc_X0.c"
+ "280 2 insn_test_v2addsc_X1.c"
+ "281 1 insn_test_v2adiffs_X0.c"
+ "282 1 insn_test_v2avgs_X0.c"
+ "283 1 insn_test_v2cmpeq_X0.c"
+ "283 2 insn_test_v2cmpeq_X1.c"
+ "284 1 insn_test_v2cmpeqi_X0.c"
+ "284 2 insn_test_v2cmpeqi_X1.c"
+ "285 1 insn_test_v2cmples_X0.c"
+ "285 2 insn_test_v2cmples_X1.c"
+ "286 1 insn_test_v2cmpleu_X0.c"
+ "286 2 insn_test_v2cmpleu_X1.c"
+ "287 1 insn_test_v2cmplts_X0.c"
+ "287 2 insn_test_v2cmplts_X1.c"
+ "288 1 insn_test_v2cmpltsi_X0.c"
+ "288 2 insn_test_v2cmpltsi_X1.c"
+ "289 1 insn_test_v2cmpltu_X0.c"
+ "289 2 insn_test_v2cmpltu_X1.c"
+ "290 1 insn_test_v2cmpltui_X0.c"
+ "290 2 insn_test_v2cmpltui_X1.c"
+ "291 1 insn_test_v2cmpne_X0.c"
+ "291 2 insn_test_v2cmpne_X1.c"
+ "292 1 insn_test_v2dotp_X0.c"
+ "293 1 insn_test_v2dotpa_X0.c"
+ "294 1 insn_test_v2int_h_X0.c"
+ "294 2 insn_test_v2int_h_X1.c"
+ "295 1 insn_test_v2int_l_X0.c"
+ "295 2 insn_test_v2int_l_X1.c"
+ "296 1 insn_test_v2maxs_X0.c"
+ "296 2 insn_test_v2maxs_X1.c"
+ "297 1 insn_test_v2maxsi_X0.c"
+ "297 2 insn_test_v2maxsi_X1.c"
+ "298 1 insn_test_v2mins_X0.c"
+ "298 2 insn_test_v2mins_X1.c"
+ "299 1 insn_test_v2minsi_X0.c"
+ "299 2 insn_test_v2minsi_X1.c"
+ "300 1 insn_test_v2mnz_X0.c"
+ "300 2 insn_test_v2mnz_X1.c"
+ "301 1 insn_test_v2mulfsc_X0.c"
+ "302 1 insn_test_v2muls_X0.c"
+ "303 1 insn_test_v2mults_X0.c"
+ "304 1 insn_test_v2mz_X0.c"
+ "304 2 insn_test_v2mz_X1.c"
+ "305 1 insn_test_v2packh_X0.c"
+ "305 2 insn_test_v2packh_X1.c"
+ "306 1 insn_test_v2packl_X0.c"
+ "306 2 insn_test_v2packl_X1.c"
+ "307 1 insn_test_v2packuc_X0.c"
+ "307 2 insn_test_v2packuc_X1.c"
+ "308 1 insn_test_v2sadas_X0.c"
+ "309 1 insn_test_v2sadau_X0.c"
+ "310 1 insn_test_v2sads_X0.c"
+ "311 1 insn_test_v2sadu_X0.c"
+ "312 1 insn_test_v2shl_X0.c"
+ "312 2 insn_test_v2shl_X1.c"
+ "313 1 insn_test_v2shli_X0.c"
+ "313 2 insn_test_v2shli_X1.c"
+ "314 1 insn_test_v2shlsc_X0.c"
+ "314 2 insn_test_v2shlsc_X1.c"
+ "315 1 insn_test_v2shrs_X0.c"
+ "315 2 insn_test_v2shrs_X1.c"
+ "316 1 insn_test_v2shrsi_X0.c"
+ "316 2 insn_test_v2shrsi_X1.c"
+ "317 1 insn_test_v2shru_X0.c"
+ "317 2 insn_test_v2shru_X1.c"
+ "318 1 insn_test_v2shrui_X0.c"
+ "318 2 insn_test_v2shrui_X1.c"
+ "319 1 insn_test_v2sub_X0.c"
+ "319 2 insn_test_v2sub_X1.c"
+ "320 1 insn_test_v2subsc_X0.c"
+ "320 2 insn_test_v2subsc_X1.c"
+ "321 1 insn_test_v4add_X0.c"
+ "321 2 insn_test_v4add_X1.c"
+ "322 1 insn_test_v4addsc_X0.c"
+ "322 2 insn_test_v4addsc_X1.c"
+ "323 1 insn_test_v4int_h_X0.c"
+ "323 2 insn_test_v4int_h_X1.c"
+ "324 1 insn_test_v4int_l_X0.c"
+ "324 2 insn_test_v4int_l_X1.c"
+ "325 1 insn_test_v4packsc_X0.c"
+ "325 2 insn_test_v4packsc_X1.c"
+ "326 1 insn_test_v4shl_X0.c"
+ "326 2 insn_test_v4shl_X1.c"
+ "327 1 insn_test_v4shlsc_X0.c"
+ "327 2 insn_test_v4shlsc_X1.c"
+ "328 1 insn_test_v4shrs_X0.c"
+ "328 2 insn_test_v4shrs_X1.c"
+ "329 1 insn_test_v4shru_X0.c"
+ "329 2 insn_test_v4shru_X1.c"
+ "330 1 insn_test_v4sub_X0.c"
+ "330 2 insn_test_v4sub_X1.c"
+ "331 1 insn_test_v4subsc_X0.c"
+ "331 2 insn_test_v4subsc_X1.c"
+ "332 2 insn_test_wh64_X1.c"
+ "333 1 insn_test_xor_X0.c"
+ "333 2 insn_test_xor_X1.c"
+ "333 4 insn_test_xor_Y0.c"
+ "333 8 insn_test_xor_Y1.c"
+ "334 1 insn_test_xori_X0.c"
+ "334 2 insn_test_xori_X1.c"
+)
+
+if [ $# -gt 0 ]; then
+#fname = "$1"
+echo "generate $1"
+for f in "${FILES[@]}"
+do
+ array=(${f// / })
+ if [ ${array[2]} = $1 ]; then
+ ./gen_insn_test ${array[0]} ${array[1]} > ${array[2]}
+# cat hello.c > ${array[2]}
+ exit 0
+ fi
+done
+
+exit -1
+
+else
+
+for f in "${FILES[@]}"
+do
+ echo $i $f
+ array=(${f// / })
+ ./gen_insn_test ${array[0]} ${array[1]} > ${array[2]}
+done
+
+fi
+
+
+
projects / thirdparty / valgrind.git / commitdiff
