Add missing <any_logic>hf/bf patterns.

It will be used by copysignm3/xorsignm3/lroundmn2 expanders.

gcc/ChangeLog:

	PR target/114334
	* config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
	(MODEF248): New mode iterator.
	(ssevecmodesuffix): Hanlde BF and HF.
	* config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
	(<code><mode>3): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr114334.c: New test.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index df97a2d6270d3ba8c4b06d1d111e1c92458fa3fd..11fdc6af3faf9dd21a68dcbe9bf3ec597a74f4f4 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -543,8 +543,9 @@
 
 ;; Main data type used by the insn
 (define_attr "mode"
-  "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF,V32HF,V16HF,V8HF,
-   V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF,V4HF,V4BF,V2HF,V2BF"
+  "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF,
+   V32HF,V16HF,V8HF,V4HF,V2HF,V32BF,V16BF,V8BF,V4BF,V2BF,
+   V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF"
   (const_string "unknown"))
 
 ;; The CPU unit operations uses.
@@ -1323,6 +1324,8 @@
 ;; SSE and x87 SFmode and DFmode floating point modes
 (define_mode_iterator MODEF [SF DF])
 
+(define_mode_iterator MODEF248 [BF HF SF (DF "TARGET_SSE2")])
+
 ;; SSE floating point modes
 (define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF])
 
@@ -1347,7 +1350,8 @@
    (V64QI "b") (V32HI "w") (V16SI "d") (V8DI "q")])
 
 ;; SSE vector suffix for floating point modes
-(define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")])
+;; BF HF use same suffix as SF for logic operations.
+(define_mode_attr ssevecmodesuffix [(BF "ps") (HF "ps") (SF "ps") (DF "pd")])
 
 ;; SSE vector mode corresponding to a scalar mode
 (define_mode_attr ssevecmode
@@ -1357,7 +1361,8 @@
 
 ;; AVX512F vector mode corresponding to a scalar mode
 (define_mode_attr avx512fvecmode
-  [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")])
+  [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI")
+   (HF "V32HF") (BF "V32BF") (SF "V16SF") (DF "V8DF")])
 
 ;; Instruction suffix for REX 64bit operators.
 (define_mode_attr rex64suffix [(SI "{l}") (DI "{q}")])

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1bc614ab7027cc04f9a36fb3438f5432da2760ae..3286d3a4faccd883f5b0cdc3a9d260a176b134c0 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5125,12 +5125,12 @@
 ;; because the native instructions read the full 128-bits.
 
 (define_insn "*andnot<mode>3"
-  [(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v")
-       (and:MODEF
-         (not:MODEF
-           (match_operand:MODEF 1 "register_operand" "0,x,v,v"))
-           (match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
-  "SSE_FLOAT_MODE_P (<MODE>mode)"
+  [(set (match_operand:MODEF248 0 "register_operand" "=x,x,v,v")
+       (and:MODEF248
+         (not:MODEF248
+           (match_operand:MODEF248 1 "register_operand" "0,x,v,v"))
+           (match_operand:MODEF248 2 "register_operand" "x,x,v,v")))]
+  "TARGET_SSE"
 {
   char buf[128];
   const char *ops;
@@ -5257,11 +5257,11 @@
              (const_string "TI")))])
 
 (define_insn "<code><mode>3"
-  [(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v")
-       (any_logic:MODEF
-         (match_operand:MODEF 1 "register_operand" "%0,x,v,v")
-         (match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
-  "SSE_FLOAT_MODE_P (<MODE>mode)"
+  [(set (match_operand:MODEF248 0 "register_operand" "=x,x,v,v")
+       (any_logic:MODEF248
+         (match_operand:MODEF248 1 "register_operand" "%0,x,v,v")
+         (match_operand:MODEF248 2 "register_operand" "x,x,v,v")))]
+  "TARGET_SSE"
 {
   char buf[128];
   const char *ops;

diff --git a/gcc/testsuite/gcc.target/i386/pr114334.c b/gcc/testsuite/gcc.target/i386/pr114334.c
new file mode 100644 (file)
index 0000000..8e38e24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr114334.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mavx512fp16" } */
+
+long
+foo(_Float16 f)
+{
+  return __builtin_lroundf16(f);
+}