drm/xe: expose PAT software config to debugfs

The existing "pat" debugfs node dumps the live PAT registers. Under
SR-IOV the VF cannot touch those registers, so the file vanishes and
users lose all PAT visibility. Add a VF-safe "pat_sw_config" entry to
the VF-safe debugfs list. It prints the cached PAT table the driver
programmed, rather than poking HW, so PF and VF instances present the
same view.

This lets IGT and other tools query the PAT configuration without
carrying platform-specific tables or mirroring kernel logic.

v2: (Jonathan)
- Only append "(* = reserved entry)" to the PAT table header on Xe2+
  platforms where it actually applies.
- Deduplicate the PTA/ATS mode printing by introducing the small
  drm_printf_pat_mode() helper macro.

v3: (Matt)
- Print IDX[XE_CACHE_NONE_COMPRESSION] on every Xe2+ platform so the
  dump always reflects the value the driver might use (even if it defaults
  to 0) and future IP revisions don’t need extra condition tweaks.

v4:
- Drop the drm_printf_pat_mode macro and introduce a real helper
  xe2_pat_entry_dump(). (Jani)
- Reuse the helper across all PTA/ATS/PAT dumps for xe2+ entries to keep
  output format identical.

v5: (Matt)
- Split the original patch into two: one for refactoring helpers, one for
  the new debugfs entry.

CC: Jani Nikula <jani.nikula@intel.com>
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251205070633.28072-1-x.wang@intel.com

diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index 7c3de65390443ff8d73017dd4ccee741ef3b7b89..e4f38b5150fc81e7743c3e903b6d895700ae308f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -209,6 +209,7 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
        { "default_lrc_vcs", .show = xe_gt_debugfs_show_with_rpm, .data = vcs_default_lrc },
        { "default_lrc_vecs", .show = xe_gt_debugfs_show_with_rpm, .data = vecs_default_lrc },
        { "hwconfig", .show = xe_gt_debugfs_show_with_rpm, .data = hwconfig },
+       { "pat_sw_config", .show = xe_gt_debugfs_simple_show, .data = xe_pat_dump_sw_config },
 };
 
 /* everything else should be added here */

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index beff250c7fa03faaa63d752e7967cbb8c526c3ea..6f48d34711a67ba4415afc3afb8a7f0c9f872962 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -592,3 +592,65 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
 
        return xe->pat.ops->dump(gt, p);
 }
+
+/**
+ * xe_pat_dump_sw_config() - Dump the software-configured GT PAT table into a drm printer.
+ * @gt: the &xe_gt
+ * @p: the &drm_printer
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
+{
+       struct xe_device *xe = gt_to_xe(gt);
+       char label[PAT_LABEL_LEN];
+
+       if (!xe->pat.table || !xe->pat.n_entries)
+               return -EOPNOTSUPP;
+
+       drm_printf(p, "PAT table:%s\n", GRAPHICS_VER(xe) >= 20 ? " (* = reserved entry)" : "");
+       for (u32 i = 0; i < xe->pat.n_entries; i++) {
+               u32 pat = xe->pat.table[i].value;
+
+               if (GRAPHICS_VERx100(xe) == 3511) {
+                       xe_pat_index_label(label, sizeof(label), i);
+                       xe3p_xpc_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
+               } else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
+                       xe_pat_index_label(label, sizeof(label), i);
+                       xe2_pat_entry_dump(p, label, pat, !xe->pat.table[i].valid);
+               } else if (xe->info.platform == XE_METEORLAKE) {
+                       xelpg_pat_entry_dump(p, i, pat);
+               } else if (xe->info.platform == XE_PVC) {
+                       xehpc_pat_entry_dump(p, i, pat);
+               } else if (xe->info.platform == XE_DG2 || GRAPHICS_VERx100(xe) <= 1210) {
+                       xelp_pat_entry_dump(p, i, pat);
+               } else {
+                       return -EOPNOTSUPP;
+               }
+       }
+
+       if (xe->pat.pat_pta) {
+               u32 pat = xe->pat.pat_pta->value;
+
+               drm_printf(p, "Page Table Access:\n");
+               xe2_pat_entry_dump(p, "PTA_MODE", pat, false);
+       }
+
+       if (xe->pat.pat_ats) {
+               u32 pat = xe->pat.pat_ats->value;
+
+               drm_printf(p, "PCIe ATS/PASID:\n");
+               xe2_pat_entry_dump(p, "PAT_ATS ", pat, false);
+       }
+
+       drm_printf(p, "Cache Level:\n");
+       drm_printf(p, "IDX[XE_CACHE_NONE] = %d\n", xe->pat.idx[XE_CACHE_NONE]);
+       drm_printf(p, "IDX[XE_CACHE_WT] = %d\n", xe->pat.idx[XE_CACHE_WT]);
+       drm_printf(p, "IDX[XE_CACHE_WB] = %d\n", xe->pat.idx[XE_CACHE_WB]);
+       if (GRAPHICS_VER(xe) >= 20) {
+               drm_printf(p, "IDX[XE_CACHE_NONE_COMPRESSION] = %d\n",
+                          xe->pat.idx[XE_CACHE_NONE_COMPRESSION]);
+       }
+
+       return 0;
+}

diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index b8559120989ed533e713f29b0d3a199c47081742..5749a488d9a9aaa048201a440627ca34abfdd2ed 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -49,6 +49,7 @@ void xe_pat_init_early(struct xe_device *xe);
 void xe_pat_init(struct xe_gt *gt);
 
 int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
+int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p);
 
 /**
  * xe_pat_index_get_coh_mode - Extract the coherency mode for the given