Fix ICE generating uniform vector masks

Most targets have an "and" instructions for their vector mask size, but RISC-V
only has DImode "and".  Fixed by allowing wider instruction modes.

gcc/ChangeLog:

	PR target/112481
	* expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.

diff --git a/gcc/expr.cc b/gcc/expr.cc
index 3e2a678710d689ad71ee48fa145fe725bccb64d9..556bcf7ef59b13cf4bdb05f6b87569474d2d84ec 100644 (file)
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -7489,7 +7489,7 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size,
            if (maybe_ne (GET_MODE_PRECISION (mode), nunits))
              tmp = expand_binop (mode, and_optab, tmp,
                                  GEN_INT ((1 << nunits) - 1), target,
-                                 true, OPTAB_DIRECT);
+                                 true, OPTAB_WIDEN);
            if (tmp != target)
              emit_move_insn (target, tmp);
            break;