[PowerPC64] Use 32-bit offset to load data

diff --git a/powerpc64/README b/powerpc64/README
index 7301953b0b6b6d7e8af6a9a364c7a102e26cdfb5..9083d898cdbb2d0b6855c818ad99a96effe7045c 100644 (file)
--- a/powerpc64/README
+++ b/powerpc64/README
@@ -34,14 +34,16 @@ VR20:VR31 Nonvolatile (extended ABI mode) their values are preserved
 
 Addressing memory
 
-There are many ways to reference data, in the sake of writing
-position-independent code the current implementation uses GOT-indirect
+There are many ways to reference data, to maintain support of
+position-independent code the current implementations use GOT-indirect
 addressing (Accessing data through the global offset table):
 1. Define data in .data section
 2. Load the address of data into register from the global offset table
-   e.g. ld 7, my_var@got(2)
+   Use 32-bit offset (medium or large code model) to get maximum addressing 
+   reach of 4 GB e.g. addis r7, r2, my_var@got@ha
+                      ld r7, my_var@got@l(r7)
 3. Use the address to load the value of data into register
-   e.g. ld 3, 0(7)
+   e.g. ld r3, 0(r7)
 Refer to [2] for more information about referencing data
 
 VSX instructions "lxvd2x/stxvd2x" are used to load and store data to

diff --git a/powerpc64/machine.m4 b/powerpc64/machine.m4
index e23832017461e7844630e4f05c9bcd0a0f55efca..187a49b8155841b9442cc72e656d15446ed17902 100644 (file)
--- a/powerpc64/machine.m4
+++ b/powerpc64/machine.m4
@@ -34,7 +34,8 @@ C used to obtain the effective address of
 C DATA_SRC storage.
 C DATA_LOAD_VEC(VEC_DST, DATA_SRC, GPR)
 define(`DATA_LOAD_VEC',
-`ld $3,$2@got(r2)
+`addis $3,r2,$2@got@ha
+ld $3,$2@got@l($3)
 lvx $1,0,$3')
 
 dnl  Usage: r0 ... r31, cr0 ... cr7

diff --git a/powerpc64/p7/chacha-4core.asm b/powerpc64/p7/chacha-4core.asm
index ed1445dddacfa152318dbcbb09c44b9ff3b8a7cf..e387006346bd30bc3bc0d79f948934479cf2d6a7 100644 (file)
--- a/powerpc64/p7/chacha-4core.asm
+++ b/powerpc64/p7/chacha-4core.asm
@@ -168,7 +168,8 @@ C Load state and splat
        vspltw  v15, v12, 3
        vspltw  v12, v12, 0
 
-       ld      r9, .Lcnts@got(r2)
+       addis   r9, r2, .Lcnts@got@ha
+       ld      r9, .Lcnts@got@l(r9)
        lxvw4x  VSR(T0), 0, r9  C increments
        vaddcuw T1, v12, T0     C compute carry-out
        vadduwm v12, v12, T0    C low adds