switch (operands[i])
{
- case AARCH64_OPND_Wt:
- po_int_reg_or_fail (REG_TYPE_R_32);
- break;
-
case AARCH64_OPND_Rsz:
case AARCH64_OPND_Rsz2:
case AARCH64_OPND_Rd:
.*: e2801be4 ldursw x4, \[sp, #1\]
.*: e2810be4 ldursw x4, \[sp, #16\]
.*: e28ffbe4 ldursw x4, \[sp, #255\]
+.*: 427ffd9f ldar wzr, \[x12\]
+.*: 427fffff ldar wzr, \[sp\]
+.*: 423ffd9f stlr wzr, \[x12\]
+.*: 423fffff stlr wzr, \[sp\]
+.*: 427f7d9f ldarb wzr, \[x12\]
+.*: 427f7fff ldarb wzr, \[sp\]
+.*: 423f7d9f stlrb wzr, \[x12\]
+.*: 423f7fff stlrb wzr, \[sp\]
+.*: 8260099f ldr wzr, \[x12\]
+.*: 8260499f ldr wzr, \[x12, #16\]
+.*: 82ea63ff ldr wzr, \[sp, x10\]
+.*: 82600d9f ldr xzr, \[x12\]
+.*: 82602d9f ldr xzr, \[x12, #16\]
+.*: 82ea67ff ldr xzr, \[sp, x10\]
+.*: 8240099f str wzr, \[x12\]
+.*: 8240499f str wzr, \[x12, #16\]
+.*: 82aa63ff str wzr, \[sp, x10\]
+.*: 82400d9f str xzr, \[x12\]
+.*: 82402d9f str xzr, \[x12, #16\]
+.*: 82aa67ff str xzr, \[sp, x10\]
+.*: e280059f ldur wzr, \[x12\]
+.*: e281059f ldur wzr, \[x12, #16\]
+.*: e28017ff ldur wzr, \[sp, #1\]
+.*: e2c0059f ldur xzr, \[x12\]
+.*: e2c1059f ldur xzr, \[x12, #16\]
+.*: e2c017ff ldur xzr, \[sp, #1\]
+.*: e280019f stur wzr, \[x12\]
+.*: e281019f stur wzr, \[x12, #16\]
+.*: e28013ff stur wzr, \[sp, #1\]
+.*: e2c0019f stur xzr, \[x12\]
+.*: e2c1019f stur xzr, \[x12, #16\]
+.*: e2c013ff stur xzr, \[sp, #1\]
+.*: 8260059f ldrb wzr, \[x12\]
+.*: 8261059f ldrb wzr, \[x12, #16\]
+.*: 82ca63ff ldrb wzr, \[sp, x10\]
+.*: e2000d9f ldursb wzr, \[x12\]
+.*: e2010d9f ldursb wzr, \[x12, #16\]
+.*: 82ca67ff ldrsb wzr, \[sp, x10\]
+.*: 8240059f strb wzr, \[x12\]
+.*: 8241059f strb wzr, \[x12, #16\]
+.*: 828a63ff strb wzr, \[sp, x10\]
+.*: e200099f ldursb xzr, \[x12\]
+.*: e201099f ldursb xzr, \[x12, #16\]
+.*: 828a67ff ldrsb xzr, \[sp, x10\]
+.*: e200059f ldurb wzr, \[x12\]
+.*: e201059f ldurb wzr, \[x12, #16\]
+.*: e20017ff ldurb wzr, \[sp, #1\]
+.*: e2000d9f ldursb wzr, \[x12\]
+.*: e2010d9f ldursb wzr, \[x12, #16\]
+.*: e2001fff ldursb wzr, \[sp, #1\]
+.*: e200019f sturb wzr, \[x12\]
+.*: e201019f sturb wzr, \[x12, #16\]
+.*: e20013ff sturb wzr, \[sp, #1\]
+.*: e200099f ldursb xzr, \[x12\]
+.*: e201099f ldursb xzr, \[x12, #16\]
+.*: e2001bff ldursb xzr, \[sp, #1\]
+.*: e240059f ldurh wzr, \[x12\]
+.*: e241059f ldurh wzr, \[x12, #16\]
+.*: 82ca6fff ldrh wzr, \[sp, x10\]
+.*: e2400d9f ldursh wzr, \[x12\]
+.*: e2410d9f ldursh wzr, \[x12, #16\]
+.*: 82ca6bff ldrsh wzr, \[sp, x10\]
+.*: e240019f sturh wzr, \[x12\]
+.*: e241019f sturh wzr, \[x12, #16\]
+.*: 828a6fff strh wzr, \[sp, x10\]
+.*: e240099f ldursh xzr, \[x12\]
+.*: e241099f ldursh xzr, \[x12, #16\]
+.*: 828a6bff ldrsh xzr, \[sp, x10\]
+.*: e240059f ldurh wzr, \[x12\]
+.*: e241059f ldurh wzr, \[x12, #16\]
+.*: e24017ff ldurh wzr, \[sp, #1\]
+.*: e2400d9f ldursh wzr, \[x12\]
+.*: e2410d9f ldursh wzr, \[x12, #16\]
+.*: e2401fff ldursh wzr, \[sp, #1\]
+.*: e240019f sturh wzr, \[x12\]
+.*: e241019f sturh wzr, \[x12, #16\]
+.*: e24013ff sturh wzr, \[sp, #1\]
+.*: e240099f ldursh xzr, \[x12\]
+.*: e241099f ldursh xzr, \[x12, #16\]
+.*: e2401bff ldursh xzr, \[sp, #1\]
.*: e2801be4 ldursw x4, \[csp, #1\]
.*: e2810be4 ldursw x4, \[csp, #16\]
.*: e28ffbe4 ldursw x4, \[csp, #255\]
+.*: 427ffebf ldar wzr, \[c21\]
+.*: 427fffff ldar wzr, \[csp\]
+.*: 423ffebf stlr wzr, \[c21\]
+.*: 423fffff stlr wzr, \[csp\]
+.*: 427f7ebf ldarb wzr, \[c21\]
+.*: 427f7fff ldarb wzr, \[csp\]
+.*: 423f7ebf stlrb wzr, \[c21\]
+.*: 423f7fff stlrb wzr, \[csp\]
+.*: 82600abf ldr wzr, \[c21\]
+.*: 82604abf ldr wzr, \[c21, #16\]
+.*: 82ea63ff ldr wzr, \[csp, x10\]
+.*: 82600ebf ldr xzr, \[c21\]
+.*: 82602ebf ldr xzr, \[c21, #16\]
+.*: 82ea67ff ldr xzr, \[csp, x10\]
+.*: 82400abf str wzr, \[c21\]
+.*: 82404abf str wzr, \[c21, #16\]
+.*: 82aa63ff str wzr, \[csp, x10\]
+.*: 82400ebf str xzr, \[c21\]
+.*: 82402ebf str xzr, \[c21, #16\]
+.*: 82aa67ff str xzr, \[csp, x10\]
+.*: e28006bf ldur wzr, \[c21\]
+.*: e28106bf ldur wzr, \[c21, #16\]
+.*: e28017ff ldur wzr, \[csp, #1\]
+.*: e2c006bf ldur xzr, \[c21\]
+.*: e2c106bf ldur xzr, \[c21, #16\]
+.*: e2c017ff ldur xzr, \[csp, #1\]
+.*: e28002bf stur wzr, \[c21\]
+.*: e28102bf stur wzr, \[c21, #16\]
+.*: e28013ff stur wzr, \[csp, #1\]
+.*: e2c002bf stur xzr, \[c21\]
+.*: e2c102bf stur xzr, \[c21, #16\]
+.*: e2c013ff stur xzr, \[csp, #1\]
+.*: 826006bf ldrb wzr, \[c21\]
+.*: 826106bf ldrb wzr, \[c21, #16\]
+.*: 82ca63ff ldrb wzr, \[csp, x10\]
+.*: e2000ebf ldursb wzr, \[c21\]
+.*: e2010ebf ldursb wzr, \[c21, #16\]
+.*: 82ca67ff ldrsb wzr, \[csp, x10\]
+.*: 824006bf strb wzr, \[c21\]
+.*: 824106bf strb wzr, \[c21, #16\]
+.*: 828a63ff strb wzr, \[csp, x10\]
+.*: e2000abf ldursb xzr, \[c21\]
+.*: e2010abf ldursb xzr, \[c21, #16\]
+.*: 828a67ff ldrsb xzr, \[csp, x10\]
+.*: e20006bf ldurb wzr, \[c21\]
+.*: e20106bf ldurb wzr, \[c21, #16\]
+.*: e20017ff ldurb wzr, \[csp, #1\]
+.*: e2000ebf ldursb wzr, \[c21\]
+.*: e2010ebf ldursb wzr, \[c21, #16\]
+.*: e2001fff ldursb wzr, \[csp, #1\]
+.*: e20002bf sturb wzr, \[c21\]
+.*: e20102bf sturb wzr, \[c21, #16\]
+.*: e20013ff sturb wzr, \[csp, #1\]
+.*: e2000abf ldursb xzr, \[c21\]
+.*: e2010abf ldursb xzr, \[c21, #16\]
+.*: e2001bff ldursb xzr, \[csp, #1\]
+.*: e24006bf ldurh wzr, \[c21\]
+.*: e24106bf ldurh wzr, \[c21, #16\]
+.*: 82ca6fff ldrh wzr, \[csp, x10\]
+.*: e2400ebf ldursh wzr, \[c21\]
+.*: e2410ebf ldursh wzr, \[c21, #16\]
+.*: 82ca6bff ldrsh wzr, \[csp, x10\]
+.*: e24002bf sturh wzr, \[c21\]
+.*: e24102bf sturh wzr, \[c21, #16\]
+.*: 828a6fff strh wzr, \[csp, x10\]
+.*: e2400abf ldursh xzr, \[c21\]
+.*: e2410abf ldursh xzr, \[c21, #16\]
+.*: 828a6bff ldrsh xzr, \[csp, x10\]
+.*: e24006bf ldurh wzr, \[c21\]
+.*: e24106bf ldurh wzr, \[c21, #16\]
+.*: e24017ff ldurh wzr, \[csp, #1\]
+.*: e2400ebf ldursh wzr, \[c21\]
+.*: e2410ebf ldursh wzr, \[c21, #16\]
+.*: e2401fff ldursh wzr, \[csp, #1\]
+.*: e24002bf sturh wzr, \[c21\]
+.*: e24102bf sturh wzr, \[c21, #16\]
+.*: e24013ff sturh wzr, \[csp, #1\]
+.*: e2400abf ldursh xzr, \[c21\]
+.*: e2410abf ldursh xzr, \[c21, #16\]
+.*: e2401bff ldursh xzr, \[csp, #1\]
morello_alt_narrow_simm9 ALTVAREG
morello_alt_narrow_simm9 ALTSP
+
+ .macro morello_alt_zero_basic, op, reg
+ \op \reg, [ALTVAREG]
+ \op \reg, [ALTSP]
+ .endm
+
+ .macro morello_alt_zero_general, op, reg
+ \op \reg, [ALTVAREG]
+ \op \reg, [ALTVAREG, #16]
+ \op \reg, [ALTSP, x10]
+ .endm
+
+ .macro morello_alt_zero_unscaled, op, reg
+ \op \reg, [ALTVAREG]
+ \op \reg, [ALTVAREG, #16]
+ \op \reg, [ALTSP, #1]
+ .endm
+
+ .irp op, ldar, stlr, ldarb, stlrb
+ morello_alt_zero_basic \op, wzr
+ .endr
+
+ .irp op, ldr, str
+ morello_alt_zero_general \op, wzr
+ morello_alt_zero_general \op, xzr
+ .endr
+
+ .irp op, ldur, stur
+ morello_alt_zero_unscaled \op, wzr
+ morello_alt_zero_unscaled \op, xzr
+ .endr
+
+ .irp size, b, h
+ .irp op, ldr\size, ldrs\size, str\size
+ morello_alt_zero_general \op, wzr
+ .endr
+ morello_alt_zero_general ldrs\size, xzr
+ .irp op, ldur\size, ldurs\size, stur\size
+ morello_alt_zero_unscaled \op, wzr
+ .endr
+ morello_alt_zero_unscaled ldurs\size, xzr
+ .endr
AARCH64_OPND_Rn, /* Integer register as source. */
AARCH64_OPND_Rm, /* Integer register as source. */
AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
- AARCH64_OPND_Wt, /* 32-bit integer register used in ld/st
- instructions. */
AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */
AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
case 11:
case 12:
case 13:
- case 14:
+ case 17:
case 18:
case 19:
case 20:
- case 21:
+ case 22:
case 23:
case 24:
case 25:
case 30:
case 31:
case 32:
- case 33:
+ case 168:
case 169:
case 170:
case 171:
case 175:
case 176:
case 177:
- case 178:
+ case 192:
case 193:
case 194:
case 195:
case 198:
case 199:
case 200:
- case 201:
- case 207:
- case 210:
+ case 206:
+ case 209:
+ case 211:
case 212:
- case 213:
- case 216:
+ case 215:
+ case 227:
case 228:
case 229:
case 230:
case 233:
case 234:
case 235:
- case 236:
- case 257:
+ case 256:
return aarch64_ins_regno (self, info, code, inst, errors);
- case 16:
- case 240:
+ case 15:
+ case 239:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
- case 17:
+ case 16:
return aarch64_ins_reg_shifted (self, info, code, inst, errors);
- case 22:
+ case 21:
return aarch64_ins_ft (self, info, code, inst, errors);
+ case 33:
case 34:
case 35:
case 36:
- case 37:
- case 224:
+ case 223:
return aarch64_ins_reglane (self, info, code, inst, errors);
- case 38:
+ case 37:
return aarch64_ins_reglist (self, info, code, inst, errors);
- case 39:
+ case 38:
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
- case 40:
+ case 39:
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
- case 41:
+ case 40:
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
+ case 41:
case 42:
case 43:
case 44:
- case 45:
+ case 54:
case 55:
case 56:
case 57:
case 68:
case 69:
case 70:
- case 71:
+ case 81:
case 82:
case 83:
case 84:
case 85:
- case 86:
- case 166:
- case 168:
+ case 165:
+ case 167:
+ case 184:
case 185:
case 186:
case 187:
case 189:
case 190:
case 191:
- case 192:
- case 217:
- case 223:
- case 244:
- case 252:
- case 256:
+ case 216:
+ case 222:
+ case 243:
+ case 251:
+ case 255:
return aarch64_ins_imm (self, info, code, inst, errors);
+ case 45:
case 46:
- case 47:
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
+ case 47:
case 48:
case 49:
- case 50:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
- case 54:
- case 156:
+ case 53:
+ case 155:
return aarch64_ins_fpimm (self, info, code, inst, errors);
- case 72:
- case 164:
+ case 71:
+ case 163:
return aarch64_ins_limm (self, info, code, inst, errors);
- case 73:
- case 243:
- case 245:
+ case 72:
+ case 242:
+ case 244:
return aarch64_ins_aimm (self, info, code, inst, errors);
- case 74:
+ case 73:
return aarch64_ins_imm_half (self, info, code, inst, errors);
- case 75:
+ case 74:
return aarch64_ins_fbits (self, info, code, inst, errors);
+ case 76:
case 77:
+ case 160:
+ return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 78:
+ case 159:
case 161:
- return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
- case 79:
- case 160:
- case 162:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
+ case 79:
case 80:
- case 81:
return aarch64_ins_cond (self, info, code, inst, errors);
- case 87:
- case 96:
- case 249:
+ case 86:
+ case 95:
+ case 248:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
- case 88:
- case 254:
+ case 87:
+ case 253:
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+ case 88:
case 89:
case 90:
- case 91:
- case 93:
- case 95:
- case 248:
+ case 92:
+ case 94:
+ case 247:
+ case 249:
case 250:
- case 251:
- case 255:
+ case 254:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
- case 92:
+ case 91:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
- case 94:
- case 253:
+ case 93:
+ case 252:
return aarch64_ins_addr_uimm (self, info, code, inst, errors);
- case 97:
+ case 96:
return aarch64_ins_addr_offset (self, info, code, inst, errors);
- case 98:
+ case 97:
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
- case 99:
+ case 98:
return aarch64_ins_sysreg (self, info, code, inst, errors);
- case 100:
+ case 99:
return aarch64_ins_pstatefield (self, info, code, inst, errors);
+ case 100:
case 101:
case 102:
case 103:
case 104:
- case 105:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
- case 106:
- case 108:
- return aarch64_ins_barrier (self, info, code, inst, errors);
+ case 105:
case 107:
+ return aarch64_ins_barrier (self, info, code, inst, errors);
+ case 106:
return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
- case 109:
+ case 108:
return aarch64_ins_prfop (self, info, code, inst, errors);
- case 110:
+ case 109:
return aarch64_ins_none (self, info, code, inst, errors);
- case 111:
+ case 110:
return aarch64_ins_hint (self, info, code, inst, errors);
+ case 111:
case 112:
- case 113:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
+ case 113:
case 114:
case 115:
case 116:
- case 117:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
- case 118:
+ case 117:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
- case 119:
+ case 118:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ case 119:
case 120:
case 121:
case 122:
- case 123:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
+ case 123:
case 124:
case 125:
case 126:
case 135:
case 136:
case 137:
- case 138:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
+ case 138:
case 139:
case 140:
case 141:
case 143:
case 144:
case 145:
- case 146:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
+ case 146:
case 147:
case 148:
case 149:
- case 150:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
- case 151:
+ case 150:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
- case 152:
+ case 151:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
- case 153:
+ case 152:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
- case 154:
+ case 153:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
- case 155:
+ case 154:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 157:
+ case 156:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
- case 158:
+ case 157:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
- case 159:
+ case 158:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 163:
+ case 162:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 165:
+ case 164:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 167:
+ case 166:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
+ case 178:
case 179:
case 180:
- case 181:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
+ case 181:
case 182:
case 183:
- case 184:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
+ case 201:
case 202:
case 203:
case 204:
case 205:
- case 206:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 208:
+ case 207:
return aarch64_ins_sve_index (self, info, code, inst, errors);
- case 209:
- case 211:
+ case 208:
+ case 210:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
+ case 213:
case 214:
- case 215:
- case 218:
+ case 217:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 219:
+ case 218:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
- case 220:
+ case 219:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
- case 221:
+ case 220:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
- case 222:
+ case 221:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 224:
case 225:
case 226:
- case 227:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 236:
case 237:
- case 238:
return aarch64_ins_regsz (self, info, code, inst, errors);
- case 239:
+ case 238:
return aarch64_ins_fregsz (self, info, code, inst, errors);
- case 246:
+ case 245:
return aarch64_ins_perm (self, info, code, inst, errors);
- case 247:
+ case 246:
return aarch64_ins_form (self, info, code, inst, errors);
default: assert (0); abort ();
}
case 7:
case 8:
case 9:
- case 10:
+ case 11:
case 12:
case 13:
- case 14:
+ case 17:
case 18:
case 19:
case 20:
- case 21:
+ case 22:
case 23:
case 24:
case 25:
case 30:
case 31:
case 32:
- case 33:
+ case 168:
case 169:
case 170:
case 171:
case 175:
case 176:
case 177:
- case 178:
+ case 192:
case 193:
case 194:
case 195:
case 198:
case 199:
case 200:
- case 201:
- case 207:
- case 210:
+ case 206:
+ case 209:
+ case 211:
case 212:
- case 213:
- case 216:
+ case 215:
+ case 227:
case 228:
case 229:
case 230:
case 233:
case 234:
case 235:
- case 236:
return aarch64_ext_regno (self, info, code, inst, errors);
- case 11:
- case 257:
+ case 10:
+ case 256:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
- case 15:
+ case 14:
return aarch64_ext_regno_pair (self, info, code, inst, errors);
- case 16:
- case 240:
+ case 15:
+ case 239:
return aarch64_ext_reg_extended (self, info, code, inst, errors);
- case 17:
+ case 16:
return aarch64_ext_reg_shifted (self, info, code, inst, errors);
- case 22:
+ case 21:
return aarch64_ext_ft (self, info, code, inst, errors);
+ case 33:
case 34:
case 35:
case 36:
- case 37:
- case 224:
+ case 223:
return aarch64_ext_reglane (self, info, code, inst, errors);
- case 38:
+ case 37:
return aarch64_ext_reglist (self, info, code, inst, errors);
- case 39:
+ case 38:
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
- case 40:
+ case 39:
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
- case 41:
+ case 40:
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
+ case 41:
case 42:
case 43:
case 44:
- case 45:
+ case 54:
case 55:
case 56:
case 57:
case 68:
case 69:
case 70:
- case 71:
+ case 81:
case 82:
case 83:
case 84:
case 85:
- case 86:
- case 166:
- case 168:
+ case 165:
+ case 167:
+ case 184:
case 185:
case 186:
case 187:
case 189:
case 190:
case 191:
- case 192:
- case 217:
- case 223:
- case 244:
- case 252:
- case 256:
+ case 216:
+ case 222:
+ case 243:
+ case 251:
+ case 255:
return aarch64_ext_imm (self, info, code, inst, errors);
+ case 45:
case 46:
- case 47:
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
+ case 47:
case 48:
case 49:
- case 50:
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
- case 51:
+ case 50:
return aarch64_ext_shll_imm (self, info, code, inst, errors);
- case 54:
- case 156:
+ case 53:
+ case 155:
return aarch64_ext_fpimm (self, info, code, inst, errors);
- case 72:
- case 164:
+ case 71:
+ case 163:
return aarch64_ext_limm (self, info, code, inst, errors);
- case 73:
+ case 72:
return aarch64_ext_aimm (self, info, code, inst, errors);
- case 74:
+ case 73:
return aarch64_ext_imm_half (self, info, code, inst, errors);
- case 75:
+ case 74:
return aarch64_ext_fbits (self, info, code, inst, errors);
+ case 76:
case 77:
+ case 160:
+ return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 78:
+ case 159:
case 161:
- return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
- case 79:
- case 160:
- case 162:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
+ case 79:
case 80:
- case 81:
return aarch64_ext_cond (self, info, code, inst, errors);
- case 87:
- case 96:
- case 249:
+ case 86:
+ case 95:
+ case 248:
return aarch64_ext_addr_simple (self, info, code, inst, errors);
- case 88:
- case 254:
+ case 87:
+ case 253:
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
+ case 88:
case 89:
case 90:
- case 91:
- case 93:
- case 95:
- case 248:
+ case 92:
+ case 94:
+ case 247:
+ case 249:
case 250:
- case 251:
- case 255:
+ case 254:
return aarch64_ext_addr_simm (self, info, code, inst, errors);
- case 92:
+ case 91:
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
- case 94:
- case 253:
+ case 93:
+ case 252:
return aarch64_ext_addr_uimm (self, info, code, inst, errors);
- case 97:
+ case 96:
return aarch64_ext_addr_offset (self, info, code, inst, errors);
- case 98:
+ case 97:
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
- case 99:
+ case 98:
return aarch64_ext_sysreg (self, info, code, inst, errors);
- case 100:
+ case 99:
return aarch64_ext_pstatefield (self, info, code, inst, errors);
+ case 100:
case 101:
case 102:
case 103:
case 104:
- case 105:
return aarch64_ext_sysins_op (self, info, code, inst, errors);
- case 106:
- case 108:
- return aarch64_ext_barrier (self, info, code, inst, errors);
+ case 105:
case 107:
+ return aarch64_ext_barrier (self, info, code, inst, errors);
+ case 106:
return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
- case 109:
+ case 108:
return aarch64_ext_prfop (self, info, code, inst, errors);
- case 110:
+ case 109:
return aarch64_ext_none (self, info, code, inst, errors);
- case 111:
+ case 110:
return aarch64_ext_hint (self, info, code, inst, errors);
+ case 111:
case 112:
- case 113:
return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
+ case 113:
case 114:
case 115:
case 116:
- case 117:
return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
- case 118:
+ case 117:
return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
- case 119:
+ case 118:
return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ case 119:
case 120:
case 121:
case 122:
- case 123:
return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
+ case 123:
case 124:
case 125:
case 126:
case 135:
case 136:
case 137:
- case 138:
return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
+ case 138:
case 139:
case 140:
case 141:
case 143:
case 144:
case 145:
- case 146:
return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
+ case 146:
case 147:
case 148:
case 149:
- case 150:
return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
- case 151:
+ case 150:
return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
- case 152:
+ case 151:
return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
- case 153:
+ case 152:
return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
- case 154:
+ case 153:
return aarch64_ext_sve_aimm (self, info, code, inst, errors);
- case 155:
+ case 154:
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
- case 157:
+ case 156:
return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
- case 158:
+ case 157:
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
- case 159:
+ case 158:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 163:
+ case 162:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 165:
+ case 164:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 167:
+ case 166:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
+ case 178:
case 179:
case 180:
- case 181:
return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
+ case 181:
case 182:
case 183:
- case 184:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
+ case 201:
case 202:
case 203:
case 204:
case 205:
- case 206:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 208:
+ case 207:
return aarch64_ext_sve_index (self, info, code, inst, errors);
- case 209:
- case 211:
+ case 208:
+ case 210:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ case 213:
case 214:
- case 215:
- case 218:
+ case 217:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 219:
+ case 218:
return aarch64_ext_sme_za_array (self, info, code, inst, errors);
- case 220:
+ case 219:
return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
- case 221:
+ case 220:
return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
- case 222:
+ case 221:
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 224:
case 225:
case 226:
- case 227:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 236:
case 237:
- case 238:
return aarch64_ext_regsz (self, info, code, inst, errors);
- case 239:
+ case 238:
return aarch64_ext_fregsz (self, info, code, inst, errors);
+ case 240:
case 241:
- case 242:
return aarch64_ext_a64c_immv (self, info, code, inst, errors);
- case 243:
+ case 242:
return aarch64_ext_a64c_aimm (self, info, code, inst, errors);
- case 245:
+ case 244:
return aarch64_ext_a64c_imm6 (self, info, code, inst, errors);
- case 246:
+ case 245:
return aarch64_ext_perm (self, info, code, inst, errors);
- case 247:
+ case 246:
return aarch64_ext_form (self, info, code, inst, errors);
default: assert (0); abort ();
}
{AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Wt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a 32-bit integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"},
case AARCH64_OPND_Rn:
case AARCH64_OPND_Rm:
case AARCH64_OPND_Rt:
- case AARCH64_OPND_Wt:
case AARCH64_OPND_Rt2:
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
/* Load/stores with alternate base, i.e. [<Cn|CSP>] in A64 mode and [<Xn|SP>] in C64 mode. */
A64C_INSN ("ldar", 0x425f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_CAPADDR, 0),
- A64C_INSN ("ldar", 0x427ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
- A64C_INSN ("ldarb", 0x427f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+ A64C_INSN ("ldar", 0x427ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+ A64C_INSN ("ldarb", 0x427f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
A64C_INSN ("stlr", 0x421f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
- A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
- A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+ A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
+ A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
A64C_INSN ("ldr", 0x82600000, 0xffe00c00, ldst_altbase, OP_LDR_POS_AC, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
A64C_INSN ("ldr", 0x82600800, 0xffe00800, ldst_altbase, OP_LDR_POS_AX, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
A64C_INSN ("ldr", 0xc2e00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_REGOFF), QL2_A64C_CA_CAPADDR, 0),
A64C_INSN ("stur", 0xe2200000, 0xff200c00, ldst_altbase, OP_STURFP_POS_A, OP2 (Fsz, CAPADDR_SIMM9), QL_S_2SAME, F_HAS_ALIAS | F_P1),
A64C_INSN ("stur", 0xe2200800, 0xffe00c00, ldst_altbase, OP_STURFPQ_POS_A, OP2 (St, CAPADDR_SIMM9), QL_I2SAMEQ, F_HAS_ALIAS | F_P1),
- A64C_INSN ("ldrb", 0x82600400, 0xffe00c00, ldst_altbase, OP_LDRB_POS_A, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
- A64C_INSN ("ldrb", 0x82c00000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
- A64C_INSN ("strb", 0x82400400, 0xffe00c00, ldst_altbase, OP_STRB_POS_A, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
- A64C_INSN ("strb", 0x82800000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
+ A64C_INSN ("ldrb", 0x82600400, 0xffe00c00, ldst_altbase, OP_LDRB_POS_A, OP2 (Rt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
+ A64C_INSN ("ldrb", 0x82c00000, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
+ A64C_INSN ("strb", 0x82400400, 0xffe00c00, ldst_altbase, OP_STRB_POS_A, OP2 (Rt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
+ A64C_INSN ("strb", 0x82800000, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
- A64C_INSN ("ldrsb", 0x82c00400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
+ A64C_INSN ("ldrsb", 0x82c00400, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
A64C_INSN ("ldrsb", 0x82800400, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_X_ADDR, 0),
- A64C_INSN ("ldrsh", 0x82c00800, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
+ A64C_INSN ("ldrsh", 0x82c00800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
A64C_INSN ("ldrsh", 0x82800800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_X_ADDR, 0),
/* These are aliases of LDURS[BHW]: */
- A64C_INSN ("ldrsb", 0xe2000c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, F_ALIAS),
+ A64C_INSN ("ldrsb", 0xe2000c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, F_ALIAS),
A64C_INSN ("ldrsb", 0xe2000800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_ALIAS),
- A64C_INSN ("ldrsh", 0xe2400c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, F_ALIAS),
+ A64C_INSN ("ldrsh", 0xe2400c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, F_ALIAS),
A64C_INSN ("ldrsh", 0xe2400800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_ALIAS),
A64C_INSN ("ldrsw", 0xe2800800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_ALIAS),
- A64C_INSN ("ldursb", 0xe2000c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, F_HAS_ALIAS | F_P1),
+ A64C_INSN ("ldursb", 0xe2000c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, F_HAS_ALIAS | F_P1),
A64C_INSN ("ldursb", 0xe2000800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_HAS_ALIAS | F_P1),
- A64C_INSN ("ldursh", 0xe2400c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, F_HAS_ALIAS | F_P1),
+ A64C_INSN ("ldursh", 0xe2400c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, F_HAS_ALIAS | F_P1),
A64C_INSN ("ldursh", 0xe2400800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_HAS_ALIAS | F_P1),
A64C_INSN ("ldursw", 0xe2800800, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_X_ADDR, F_HAS_ALIAS | F_P1),
- A64C_INSN ("ldrh", 0x82c00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
- A64C_INSN ("strh", 0x82800c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
+ A64C_INSN ("ldrh", 0x82c00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
+ A64C_INSN ("strh", 0x82800c00, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
/* These are aliases of LDURH and STURH: */
- A64C_INSN ("ldrh", 0xe2400400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, F_ALIAS),
- A64C_INSN ("strh", 0xe2400000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, F_ALIAS),
+ A64C_INSN ("ldrh", 0xe2400400, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_H_ADDR, F_ALIAS),
+ A64C_INSN ("strh", 0xe2400000, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_H_ADDR, F_ALIAS),
- A64C_INSN ("ldurb", 0xe2000400, 0xffe00c00, ldst_altbase, OP_LDURB_A, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
- A64C_INSN ("sturb", 0xe2000000, 0xffe00c00, ldst_altbase, OP_STURB_A, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
- A64C_INSN ("ldurh", 0xe2400400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, F_HAS_ALIAS | F_P1),
- A64C_INSN ("sturh", 0xe2400000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, F_HAS_ALIAS | F_P1),
+ A64C_INSN ("ldurb", 0xe2000400, 0xffe00c00, ldst_altbase, OP_LDURB_A, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
+ A64C_INSN ("sturb", 0xe2000000, 0xffe00c00, ldst_altbase, OP_STURB_A, OP2 (Rt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
+ A64C_INSN ("ldurh", 0xe2400400, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_H_ADDR, F_HAS_ALIAS | F_P1),
+ A64C_INSN ("sturh", 0xe2400000, 0xffe00c00, ldst_altbase, 0, OP2 (Rt, CAPADDR_SIMM9), QL2_H_ADDR, F_HAS_ALIAS | F_P1),
A64C_INSN ("ret", 0xc2c25000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, F_OPD0_OPT | F_DEFAULT (30)),
A64C_INSN ("retr", 0xc2c25003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \
Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
- Y(INT_REG, regno, "Wt", 0, F(FLD_Rt), "a 32-bit integer register") \
Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \
Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \
projects / thirdparty / binutils-gdb.git / commitdiff
