Usually, the supply is around 1.2 V, not 1.8 V, and also correct wording.
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.2V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdd-csiphy-0p8-supply:
description:
- Phandle to a 0.8V regulator supply to a PHY.
+ 0.8V supply to a PHY.
vdd-csiphy-1p2-supply:
description:
- Phandle to 1.2V regulator supply to a PHY.
+ 1.2V supply to a PHY.
ports:
$ref: /schemas/graph.yaml#/properties/ports