drm/amd/display: Fix DP MST timeslot issue when fallback happened

[ Upstream commit 20c6168b3c8aadef7d2853c925d99eb546bd5e1c ]

[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.

[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0c52506b367de9d7d7b961081faa929e05c3c754..b4203a812c4bec1c060171e9c430b6d9483cbe13 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2857,8 +2857,14 @@ bool perform_link_training_with_retries(
                                                skip_video_pattern);
 
                                /* Transmit idle pattern once training successful. */
-                               if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low)
+                               if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
                                        dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
+                                       /* Update verified link settings to current one
+                                        * Because DPIA LT might fallback to lower link setting.
+                                        */
+                                       link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
+                                       link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
+                               }
                        } else {
                                status = dc_link_dp_perform_link_training(link,
                                                &pipe_ctx->link_res,