]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: coex: make coex scoreboard as chip info
authorPing-Ke Shih <pkshih@realtek.com>
Thu, 8 Jan 2026 12:03:08 +0000 (20:03 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Tue, 13 Jan 2026 02:18:00 +0000 (10:18 +0800)
The coex scoreboard is to exchange WiFi and BT profiles, and the coming
chip 8922D changes the design including extend to two scoreboards and
individual register for cfg/get. Follow the changes to abstract current
code, but not change logic for existing chips at all.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260108120320.2217402-2-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/reg.h
drivers/net/wireless/realtek/rtw89/rtw8851b.c
drivers/net/wireless/realtek/rtw89/rtw8852a.c
drivers/net/wireless/realtek/rtw89/rtw8852b.c
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8922a.c

index 40527354c95d54057def73afbb10f01c5aa9a2a9..4c39c4dbaf567d447505510ef22ec136ff0d4b0e 100644 (file)
@@ -4360,6 +4360,13 @@ struct rtw89_rfkill_regs {
        struct rtw89_reg3_def mode;
 };
 
+struct rtw89_sb_regs {
+       struct {
+               u32 cfg;
+               u32 get;
+       } n[2];
+};
+
 struct rtw89_dig_regs {
        u32 seg0_pd_reg;
        u32 pd_lower_bound_mask;
@@ -4577,6 +4584,7 @@ struct rtw89_chip_info {
        u32 bss_clr_map_reg;
        const struct rtw89_rfkill_regs *rfkill_init;
        struct rtw89_reg_def rfkill_get;
+       struct rtw89_sb_regs btc_sb;
        u32 dma_ch_mask;
        const struct rtw89_edcca_regs *edcca_regs;
        const struct wiphy_wowlan_support *wowlan_stub;
index 1375ab324a8b0ef65431f09ccd384394bf7609df..1a53824f58b55718fc239d51312d203e3d41f2ae 100644 (file)
@@ -1498,6 +1498,7 @@ static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
        const struct rtw89_chip_info *chip = rtwdev->chip;
        const struct rtw89_pwr_cfg * const *cfg_seq;
        int (*cfg_func)(struct rtw89_dev *rtwdev);
+       u32 reg = chip->btc_sb.n[0].cfg;
        int ret;
 
        rtw89_mac_power_switch_boot_mode(rtwdev);
@@ -1537,14 +1538,14 @@ static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
                set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
                set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
                set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
-               rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
+               rtw89_write8(rtwdev, reg + 3, MAC_AX_NOTIFY_TP_MAJOR);
        } else {
                clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
                clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
                clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
                clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
                clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
-               rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
+               rtw89_write8(rtwdev, reg + 3, MAC_AX_NOTIFY_PWR_MAJOR);
                rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false);
                rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false);
        }
@@ -6413,9 +6414,11 @@ int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
 
 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
 {
+       const struct rtw89_chip_info *chip = rtwdev->chip;
+       u32 reg = chip->btc_sb.n[0].cfg;
        u32 fw_sb;
 
-       fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
+       fw_sb = rtw89_read32(rtwdev, reg);
        fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb);
        fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY;
        if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
@@ -6426,13 +6429,16 @@ void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
        val = B_AX_TOGGLE |
              FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
              FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb);
-       rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
+       rtw89_write32(rtwdev, reg, val);
        fsleep(1000); /* avoid BT FW loss information */
 }
 
 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
 {
-       return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
+       const struct rtw89_chip_info *chip = rtwdev->chip;
+       u32 reg = chip->btc_sb.n[0].get;
+
+       return rtw89_read32(rtwdev, reg);
 }
 
 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
index 9f963bd85f0258fc9c5f494d491c37f3ac553d67..afe13c0c5629aa2ee50c495ae6083350ec1068f8 100644 (file)
 #define B_BE_EF_DSB_EN BIT(11)
 #define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
 
+#define R_BE_SCOREBOARD 0x00AC
+#define B_BE_TOGGLE BIT(31)
+#define B_BE_DATA_LINE_MASK GENMASK(30, 0)
+
 #define R_BE_PMC_DBG_CTRL2 0x00CC
 #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
 #define B_BE_DIS_IOWRAP_TIMEOUT BIT(16)
index e06e7075173537155e64628bafe88c2d36fb4b17..0383d3b5c7bc29a7b433ea55eb0515531b7c7842 100644 (file)
@@ -2707,6 +2707,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP_V1,
        .rfkill_init            = &rtw8851b_rfkill_regs,
        .rfkill_get             = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
+       .btc_sb                 = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
        .dma_ch_mask            = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
                                  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
                                  BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
index bb12982afef794a2b670fc4dc4fbb42734939122..329fc0a7b07b0b96fdf3ad0006b213ad76b6bdf9 100644 (file)
@@ -2394,6 +2394,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP,
        .rfkill_init            = &rtw8852a_rfkill_regs,
        .rfkill_get             = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
+       .btc_sb                 = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
        .dma_ch_mask            = 0,
        .edcca_regs             = &rtw8852a_edcca_regs,
 #ifdef CONFIG_PM
index a138d89bce84ebc1ef61482f20499baff0bee4d0..f44674a39e30dc17f1706ff1507e21d1c00741b2 100644 (file)
@@ -1041,6 +1041,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP_V1,
        .rfkill_init            = &rtw8852b_rfkill_regs,
        .rfkill_get             = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
+       .btc_sb                 = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
        .dma_ch_mask            = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
                                  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
                                  BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
index 7b637483e9b4aecdfa82c51938b90009ad1e5fa7..ab60ed389ff7f6d01f9f53b3cb71143cde8ca47b 100644 (file)
@@ -878,6 +878,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP_V1,
        .rfkill_init            = &rtw8852bt_rfkill_regs,
        .rfkill_get             = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
+       .btc_sb                 = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
        .dma_ch_mask            = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
                                  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
                                  BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
index a82bbe3ec901b492ae82cba12f344782e9d909ca..d2138be3640d7e91c276f8fa835b4b839925b823 100644 (file)
@@ -3239,6 +3239,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP,
        .rfkill_init            = &rtw8852c_rfkill_regs,
        .rfkill_get             = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
+       .btc_sb                 = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
        .dma_ch_mask            = 0,
        .edcca_regs             = &rtw8852c_edcca_regs,
 #ifdef CONFIG_PM
index 041ffec9a327efe7a884c5b412a14c91a14dd063..6d2cd914e16e5badb6a25f977d41e67ba6c69b6b 100644 (file)
@@ -3005,6 +3005,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
        .bss_clr_map_reg        = R_BSS_CLR_MAP_V2,
        .rfkill_init            = &rtw8922a_rfkill_regs,
        .rfkill_get             = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
+       .btc_sb                 = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
        .dma_ch_mask            = 0,
        .edcca_regs             = &rtw8922a_edcca_regs,
 #ifdef CONFIG_PM