The assembly of these instructions is not alwasy being done correctly as
described in the following email reply.
Re: Assembling Power instructions: dcbtst/dcbt.
From: Peter Bergner <bergner at vnet dot ibm dot com>
To: Paralkar Anmol-B07584 <B07584 at freescale dot com>
Cc: "amodra at bigpond dot net dot au" <amodra at bigpond dot net dot au>, "binutils at sourceware dot org" <binutils at sourceware dot org>
Date: Fri, 13 Sep 2013 15:22:35 -0500
Subject: Re: Assembling Power instructions: dcbtst/dcbt.
Authentication-results: sourceware.org; auth=none
References: <
DC6D7B34688246489A6578981A5ADEB9302A07 at 039-SN2MPN1-012 dot 039d dot mgd dot msft dot net>
On Fri, 2013-09-13 at 18:32 +0000, Paralkar Anmol-B07584 wrote:
> Hello,
>
> Per Power ISA Version 2.07 (May 3, 2013) "4.3.2 Data Cache Instructions",
> the assembly language syntax for the dcbtst instruction (pp. 771) is:
>
> dcbtst RA,RB,TH [Category: Server]
> dcbtst TH,RA,RB [Category: Embedded]
>
> and it's layout in the object code is:
>
> +------+------+------+------+------------+---+
> | 31 | TH | RA | RB | 246(0xF6) | / |
> |0 |6 |11 |16 |21 |31 |
> +------+------+------+------+------------+---+
>
> (Analogously: dcbt pp. 770)
>
> However, GAS (as of version 2.23.52.
20130912) decides on the syntax to use based on
> processor/architecture dialect (not Power ISA Category), using the Server syntax in
> the case of POWER4 and the Embedded syntax for generic PPC or VLE.
That was a bug fixed here:
https://sourceware.org/ml/binutils/2012-11/msg00352.html
> Consequently (e.g.),
>
> dcbtst 17, 14, 6
>
> in the assembly file gets "misassembled" under -many for a user-space program on Linux:
When you only specify -many (and not one of -mpower4, -mpower5, etc.),
the assembler/disassembler will choose a default -m<CPU> value for
you. That has changed over time, but is generally one of the newer
server cpus. For example, for binutils trunk, the default is now
-mpower8 and for your 2.23.x binutils, it is -mpower7.
That should force the assembler and disassembler to assemble
the instruction using the server operand order you want, but the bug
above (which is in 2.23) basically resets it to an old cpu, so it
chooses to use the embedded/old cpu setting.
The patch from Amodra fixes the issue by manually generating the correct
hex value for the instruction rather then leaving it to the assembler to
generate the hex value from the symbolic assembly instruction name.
This is the fix for Bugzilla 324765.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13562
#include <stdint.h>
#include "tests/sys_mman.h"
#include "tests/malloc.h" // memalign16
+#include "./opcodes.h"
#define STATIC_ASSERT(e) sizeof(struct { int:-!(e); })
*/
static void test_dcbtct (void)
{
- __asm__ __volatile__ ("dcbt %0, %1, 1" : : "b" (r17), "r" (r14));
- __asm__ __volatile__ ("dcbt %0, %1, 7" : : "b" (r17), "r" (r14));
+ /* dcbt RA, RB, TH */
+ ASM_DCBT(17, 14, 1);
+ ASM_DCBT(17, 14, 7);
}
static void test_dcbtds (void)
{
- __asm__ __volatile__ ("dcbt %0, %1, 10" : : "b" (r17), "r" (r14));
- __asm__ __volatile__ ("dcbt %0, %1, 0" : : "b" (r17), "r" (r14));
- __asm__ __volatile__ ("dcbt %0, %1, 16" : : "b" (r17), "r" (r14));
+ /* dcbt RA, RB, TH */
+ ASM_DCBT(17, 14, 10);
+ ASM_DCBT(17, 14, 0);
+ ASM_DCBT(17, 14, 16);
}
static void test_dcbtst (void)
{
- __asm__ __volatile__ ("dcbtst %0, %1, 6" : : "b" (r17), "r" (r14));
- __asm__ __volatile__ ("dcbtst %0, %1, 15" : : "b" (r17), "r" (r14));
+ /* dcbtst RA, RB, TH */
+ ASM_DCBTST(17, 14, 6);
+ ASM_DCBTST(17, 14, 15);
}
--- /dev/null
+#ifndef OPCODES_H
+#define OPCODES_H
+
+/* (Along the lines of ../s390x/opcodes.h) Macro definitions to hand-assemble
+ * instructions known to cause problems with assemblers or across assembler
+ * versions.
+ *
+ * Notes:
+ *
+ * 0. Offsets used in encodings are in Valgrind (Right to Left) ordering.
+ * 1. Use register numbers, not register names in macro invocations.
+ * 2. Insert the definitions for a new instruction/instruction format in
+ * the order of the appearance of its definition in the Power ISA.
+ */
+
+/* Instruction formats:
+ */
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 15: X-FORM */
+#define X20_ASM_DIRECTIVE ".long"
+#define X20_OPCODE_OFFSET "26"
+#define X20_TH_OFFSET "21"
+#define X20_RA_OFFSET "16"
+#define X20_RB_OFFSET "11"
+#define X20_XO_OFFSET "1"
+#define X20_RES_OFFSET "0"
+
+#define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
+ X20_ASM_DIRECTIVE " " \
+ "(" #OPCODE "<<" X20_OPCODE_OFFSET ")" "+" \
+ "(" #TH "<<" X20_TH_OFFSET ")" "+" \
+ "(" #RA "<<" X20_RA_OFFSET ")" "+" \
+ "(" #RB "<<" X20_RB_OFFSET ")" "+" \
+ "(" #XO "<<" X20_XO_OFFSET ")" "+" \
+ "(" #RES "<<" X20_RES_OFFSET ")"
+
+#define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
+
+/* Instruction specifics:
+ */
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 770: dcbt (Category: Server Syntax) */
+#define DCBT_OPCODE 31
+#define DCBT_XO 278
+#define DCBT_RES 0
+#define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
+#define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 771: dcbtst (Category: Server Syntax) */
+#define DCBTST_OPCODE 31
+#define DCBTST_XO 246
+#define DCBTST_RES 0
+#define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES)
+#define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH))
+
+#endif /* OPCODES_H */
--- /dev/null
+../ppc32/opcodes.h
\ No newline at end of file
projects / thirdparty / valgrind.git / commitdiff
