clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
register controls the selection of the clock feeding the display engine.

Add clock gate support for the two CSRs.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-4-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index c62d61c3444bd40fabcc0b50929584cc1724ae95..7e88877a624518cc679cfb3bf673418207a1bc74 100644 (file)
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  */
 
+#include <dt-bindings/clock/nxp,imx94-clock.h>
 #include <dt-bindings/clock/nxp,imx95-clock.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
@@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
        .clk_reg_offset = 0,
 };
 
+static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
+       [IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
+               .name = "lvds_clk_gate",
+               .parent_names = (const char *[]){ "ldbpll", },
+               .num_parents = 1,
+               .reg = 0,
+               .bit_idx = 1,
+               .bit_width = 1,
+               .type = CLK_GATE,
+               .flags = CLK_SET_RATE_PARENT,
+               .flags2 = CLK_GATE_SET_TO_DISABLE,
+       },
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
+       .num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
+       .clk_dev_data = imx94_lvds_clk_dev_data,
+       .clk_reg_offset = 0,
+       .rpm_enabled = true,
+};
+
+static const char * const imx94_disp_engine_parents[] = {
+       "disppix", "ldb_pll_div7"
+};
+
+static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
+       [IMX94_CLK_DISPMIX_CLK_SEL] = {
+               .name = "disp_clk_sel",
+               .parent_names = imx94_disp_engine_parents,
+               .num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
+               .reg = 0,
+               .bit_idx = 1,
+               .bit_width = 1,
+               .type = CLK_MUX,
+               .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+       },
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
+       .num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
+       .clk_dev_data = imx94_dispmix_csr_clk_dev_data,
+       .clk_reg_offset = 0,
+       .rpm_enabled = true,
+};
+
 static int imx95_bc_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
@@ -467,6 +513,8 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {
 };
 
 static const struct of_device_id imx95_bc_of_match[] = {
+       { .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
+       { .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
        { .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
        { .compatible = "nxp,imx95-display-master-csr", },
        { .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },